Cypress CY7C604XX manual High Output Voltage, Vdd Port 2 or 3 Pins Current in all I/Os

Page 18

CY7C604XX

Table 11. 2.4V to 3.0V DC GPIO Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

RPU

Pull Up Resistor

 

4

5.6

8

VOH1

High Output Voltage

IOH < 10 μA, maximum of 10 mA source

Vdd - 0.2

V

 

Port 2 or 3 Pins

current in all I/Os

 

 

 

 

VOH2

High Output Voltage

IOH = 0.2 mA, maximum of 10 mA source

Vdd - 0.4

V

 

Port 2 or 3 Pins

current in all I/Os

 

 

 

 

VOH3

High Output Voltage

IOH < 10 μA, maximum of 10 mA source

Vdd - 0.2

V

 

Port 0 or 1 Pins with LDO Regulator

current in all I/Os

 

 

 

 

 

Disabled for Port 1

 

 

 

 

 

VOH4

High Output Voltage

IOH = 2 mA, maximum of 10 mA source

Vdd - 0.5

V

 

Port 0 or 1 Pins with LDO Regulator

current in all I/Os

 

 

 

 

 

Disabled for Port 1

 

 

 

 

 

VOH5A

High Output Voltage

IOH < 10 μA, Vdd > 2.4V, maximum of 20

1.50

1.80

2.10

V

 

Port 1 Pins with LDO Enabled for 1.8V

mA source current in all I/Os.

 

 

 

 

 

Out

 

 

 

 

 

VOH6A

High Output Voltage

IOH = 1 mA, Vdd > 2.4V, maximum of 20

1.20

V

 

Port 1 Pins with LDO Enabled for 1.8V

mA source current in all I/Os

 

 

 

 

 

Out

 

 

 

 

 

VOL

Low Output Voltage

IOL = 10 mA, maximum of 30 mA sink

0.75

V

 

 

current on even port pins (for example,

 

 

 

 

 

 

P0[2] and P1[4]) and 30 mA sink current

 

 

 

 

 

 

on odd port pins (for example, P0[3] and

 

 

 

 

 

 

P1[5])

 

 

 

 

VIL

Input Low Voltage

 

0.72

V

VIH

Input High Voltage

 

1.6

 

V

VH

Input Hysteresis Voltage

 

80

mV

IIL

Input Leakage (Absolute Value)

 

0.001

1

µA

CPIN

Capacitive Load on Pins

Package and pin dependent

0.5

1.7

5

pF

 

 

Temp = 25oC

 

 

 

 

Document Number: 001-12395 Rev *H

Page 18 of 30

[+] Feedback

Image 18
Contents EnCoRe FeaturesEnCoRe V LV Block Diagram Low VoltageFunctional Overview Getting Started EnCoRe V LV CoreAdditional System Resources Development Tools PSoC Designer Software SubsystemsSelect Components Configure ComponentsDesigning with PSoC Designer Organize and ConnectUnits of Measure Document ConventionsAcronyms Used Numeric NamingPin Configuration Pin Part PinoutPin Part Pinout QFN Pin No Type Name Description Vss Ground connectionP16 Digital I/O P02 Digital I/O P30 Digital I/O P32 P20 P22 P24 P26P00 Digital I/O P06 Digital I/OTop View P15 Digital I/O, I2C SDA, SPI Miso No connectionVss Supply ground Vss Supply ground No connectionVdd Supply voltage No connection P01 Digital I/ORegister Mapping Tables Register ReferenceRegister Conventions Register Conventions DescriptionName Addr 0,Hex Access Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space Name Addr 1,Hex AccessElectrical Specifications Units of Measure Symbol Unit of MeasureADC Electrical Specifications Maximum Ratings DC Electrical CharacteristicsDC Chip Level Specifications Operating ConditionsDC General Purpose I/O Specifications Vdd Port 2 or 3 Pins Current in all I/Os High Output VoltageSink current on odd port pins for Example, P03 and P15 Input Low Voltage VddInput High Voltage Vdd Input Hysteresis Voltage DC POR and LVD Specifications DC Programming SpecificationsAC Electrical Characteristics AC Chip Level SpecificationsAC General Purpose IO Specifications AC External Clock Specifications AC Programming SpecificationsAC SPI Specifications AC SPI Specifications Symbol Description Min Typ Max UnitsWidth of SS Negated Between Transmissions AC I2C Specifications Package Diagram Packaging DimensionsPin 5 x 5 x 0.55 mm QFN Package Handling 125Solder Reflow Peak Temperature Thermal ImpedancesOrdering Information Document History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions