CY7C604XX
Functional Overview | Getting Started |
The enCoRe V LV family of devices are designed to replace multiple traditional low voltage microcontroller system compo- nents with one, low cost single chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.
The architecture for this device family, as illustrated in enCoRe V LV Block Diagram, is comprised of two main areas: the CPU core and the system resources. Depending on the enCoRe V LV package, up to 36 general purpose IO (GPIO) are also included.
Enhancements over the Cypress’s legacy low voltage microcon- trollers include faster CPU at lower voltage operation, lower current consumption, twice the RAM and Flash,
The enCoRe V LV Core
The enCoRe V LV Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a
System Resources provide additional capability, such as a configurable I2C slave and SPI
Additional System Resources
System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The following statements describe the merits of each system resource:
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■The I2C slave and SPI
■In I2C slave mode, the hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device has been received.
■Low Voltage Detection (LVD) interrupts can signal the appli- cation of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.
■The 5V maximum input, 1.8, 2.5, or 3V selectable output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO.
■Standard Cypress PSoC IDE tools are available for debugging the enCoRe V LV family of parts.
The quickest way to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the enCoRe V integrated circuit and presents specific pin, register, and electrical specifications. For
For
Development Kits
Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet,
Training
Free technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.
CyPros Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various appli- cation designs that include firmware and hardware design files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at
Application Notes
Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab.
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