Cypress CY62157EV30 manual Pin Tsop I 12 mm x 18.4 mm x 1.0 mm

Page 13

CY62157EV30 MoBL®

Package Diagrams (continued)

Figure 11. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183

DIMENSIONS IN INCHES[MM] MIN.

MAX.

JEDEC # MO-142

1

0.724 [18.40]

0.787[20.00]

0.004[0.10]

0.008[0.21]

 

 

0.020[0.50]

-5°

0.028[0.70]

N

0.472[12.00]

0.047[1.20]

MAX.

0.010[0.25]

GAUGE PLANE

0.037[0.95]

0.041[1.05]

0.020[0.50]

TYP.

0.007[0.17]

0.011[0.27]

0.002[0.05]

0.006[0.15]

SEATING PLANE

0.004[0.10]

51-85183-*A

MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05445 Rev. *E

Page 13 of 14

© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

Image 13
Contents Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationProduct Portfolio Pin ConfigurationBall Vfbga Top View Following picture shows the 48-ball Vfbga pinout.3, 4Maximum Ratings Electrical CharacteristicsOperating Range CapacitanceThermal Resistance Data Retention CharacteristicsAC Test Loads and Waveforms Data Retention Waveform12Write Cycle Switching CharacteristicsRead Cycle No Address Transition Controlled19 Switching WaveformsWrite Cycle No CE1 or CE2 Controlled18, 22 Write Cycle No WE Controlled18, 22Write Cycle No BHE/BLE Controlled, OE LOW23 Write Cycle No WE Controlled, OE LOW23Truth Table Inputs/Outputs Mode PowerOrdering Information BHE BLEPin Vfbga 6 x 8 x 1 mm Package DiagramsPin Tsop II Pin Tsop I 12 mm x 18.4 mm x 1.0 mm Document History Issue Date Orig. Change Description of ChangeDocument Number REV ECN no