Cypress CY62157EV30 manual Switching Waveforms, Read Cycle No Address Transition Controlled19

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CY62157EV30 MoBL®

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[19, 20]

Figure 3. Read Cycle No. 1

tRC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 (OE Controlled)[20, 21]

 

 

 

Figure 4. Read Cycle No. 2

ADDRESS

 

 

CE1

 

tRC

 

tPD

 

 

CE2

 

tHZCE

 

 

 

tACE

 

BHE/BLE

 

 

 

tDBE

tHZBE

 

tLZBE

 

OE

 

 

 

tDOE

tHZOE

 

tLZOE

HIGH

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

 

DATA VALID

 

 

 

tLZCE

ICC

VCC

tPU

SUPPLY

50%

50%

 

ISB

CURRENT

 

Notes

19.The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.

20.WE is HIGH for read cycle.

21.Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

Document #: 38-05445 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1Product Portfolio Pin ConfigurationBall Vfbga Top View Following picture shows the 48-ball Vfbga pinout.3, 4Capacitance Electrical CharacteristicsMaximum Ratings Operating RangeData Retention Waveform12 Data Retention CharacteristicsThermal Resistance AC Test Loads and WaveformsWrite Cycle Switching CharacteristicsRead Cycle No Address Transition Controlled19 Switching WaveformsWrite Cycle No CE1 or CE2 Controlled18, 22 Write Cycle No WE Controlled18, 22Write Cycle No BHE/BLE Controlled, OE LOW23 Write Cycle No WE Controlled, OE LOW23BHE BLE Inputs/Outputs Mode PowerTruth Table Ordering InformationPin Vfbga 6 x 8 x 1 mm Package DiagramsPin Tsop II Pin Tsop I 12 mm x 18.4 mm x 1.0 mm REV ECN no Issue Date Orig. Change Description of ChangeDocument History Document Number