Cypress CY62157EV30 Thermal Resistance, AC Test Loads and Waveforms, Data Retention Waveform12

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CY62157EV30 MoBL®

Thermal Resistance [10]

Parameter

Description

Test Conditions

BGA

TSOP I

TSOP II

Unit

ΘJA

Thermal Resistance

Still Air, soldered on a 3 × 4.5 inch,

72

74.88

76.88

°C/W

 

(Junction to Ambient)

two-layer printed circuit board

 

 

 

 

ΘJC

Thermal Resistance

 

8.86

8.6

13.52

°C/W

 

(Junction to Case)

 

 

 

 

 

AC Test Loads and Waveforms

Figure 1. AC Test Loads and Waveforms

R1

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

VCC

 

 

 

 

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

 

90%

 

10%

 

 

 

 

 

 

90%

 

 

 

 

 

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fall Time = 1 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

R2 Rise Time = 1 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Equivalent to:

 

THÉVENIN EQUIVALENT

 

 

 

 

 

 

 

 

 

 

 

 

RTH

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

V TH

 

 

 

 

 

 

 

 

 

 

 

Parameters

2.5V

3.0V

Unit

R1

16667

1103

R2

15385

1554

RTH

8000

645

VTH

1.20

1.75

V

Data Retention Characteristics

Over the Operating Range

Parameter

Description

 

 

Conditions

 

Min

Typ [2]

Max

Unit

VDR

VCC for Data Retention

 

 

 

 

1.5

 

 

V

[9]

Data Retention Current

VCC= 1.5V, CE1 > VCC – 0.2V,

Ind’l/Auto-A

 

2

5

A

ICCDR

 

 

 

CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V

 

 

 

 

 

tCDR [10]

Chip Deselect to Data

 

 

 

 

0

 

 

ns

 

Retention Time

 

 

 

 

 

 

 

 

t [11]

Operation Recovery Time

 

 

 

 

t

 

 

ns

R

 

 

 

 

 

RC

 

 

 

Data Retention Waveform[12]

Figure 2. Data Retention Waveform

VCC

CE1 or

BHE.BLE or

CE2

VCC(min) tCDR

DATA RETENTION MODE

VDR > 1.5V

VCC(min)

tR

Notes

11.Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.

12.BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.

Document #: 38-05445 Rev. *E

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Contents Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationProduct Portfolio Pin ConfigurationBall Vfbga Top View Following picture shows the 48-ball Vfbga pinout.3, 4Maximum Ratings Electrical CharacteristicsOperating Range CapacitanceThermal Resistance Data Retention CharacteristicsAC Test Loads and Waveforms Data Retention Waveform12Write Cycle Switching CharacteristicsRead Cycle No Address Transition Controlled19 Switching WaveformsWrite Cycle No CE1 or CE2 Controlled18, 22 Write Cycle No WE Controlled18, 22Write Cycle No BHE/BLE Controlled, OE LOW23 Write Cycle No WE Controlled, OE LOW23Truth Table Inputs/Outputs Mode PowerOrdering Information BHE BLEPin Vfbga 6 x 8 x 1 mm Package DiagramsPin Tsop II Pin Tsop I 12 mm x 18.4 mm x 1.0 mm Document History Issue Date Orig. Change Description of ChangeDocument Number REV ECN no