Cypress CY62157EV30 manual Pin Tsop II

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CY62157EV30 MoBL®

Package Diagrams (continued)

Figure 10. 44-Pin TSOP II, 51-85087

51-85087-*A

Document #: 38-05445 Rev. *E

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Contents Features Logic Block DiagramFunctional Description1 Cypress Semiconductor CorporationPin Configuration Product PortfolioFollowing picture shows the 48-ball Vfbga pinout.3, 4 Ball Vfbga Top ViewElectrical Characteristics Maximum RatingsOperating Range CapacitanceData Retention Characteristics Thermal ResistanceAC Test Loads and Waveforms Data Retention Waveform12Switching Characteristics Write CycleSwitching Waveforms Read Cycle No Address Transition Controlled19Write Cycle No WE Controlled18, 22 Write Cycle No CE1 or CE2 Controlled18, 22Write Cycle No WE Controlled, OE LOW23 Write Cycle No BHE/BLE Controlled, OE LOW23Inputs/Outputs Mode Power Truth TableOrdering Information BHE BLEPackage Diagrams Pin Vfbga 6 x 8 x 1 mmPin Tsop II Pin Tsop I 12 mm x 18.4 mm x 1.0 mm Issue Date Orig. Change Description of Change Document HistoryDocument Number REV ECN no