Cypress CY62157EV30 manual Features, Functional Description1, Logic Block Diagram

CY62157EV30 MoBL®

8-Mbit (512K x 16) Static RAM

Features

•TSOP I package configurable as 512K x 16 or as 1M x 8

SRAM

•High speed: 45 ns

•Wide voltage range: 2.20V–3.60V

•Pin compatible with CY62157DV30

•Ultra low standby power

—Typical Standby current: 2 ∝A

—Maximum Standby current: 8 ∝A (Industrial)

•Ultra low active power

—Typical active current: 1.8 mA @ f = 1 MHz

•Easy memory expansion with CE1, CE2, and OE features

•Automatic power down when deselected

•CMOS for optimum speed and power

•Available in both Pb-free and non Pb-free 48-ball VFBGA, Pb-free 44-pin TSOP II and 48-pin TSOP I packages

Functional Description[1]

The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (IO0 through IO15) are placed in a high impedance state when:

•Deselected (CE1HIGH or CE2 LOW)

•Outputs are disabled (OE HIGH)

•Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH)

•Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)

To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18).

To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 10 for a complete description of read and write modes.

Logic Block Diagram

		DATA IN DRIVERS
A10
A 9	ROWDECODER						SENSE AMPS
A 8
A 7		512K × 16 / 1M x 8
A 6
A 5			RAM Array					IO	–IO	7
A 4								0
A 3								IO8–IO15
A 2
A 1
A 0
		COLUMN DECODER
	CE2							BYTE
Power Down	CE1							BHE
		11	12	13	14	15 16 17 18		WE		CE2
Circuit										CE1
	BHE	A A A A A A A A						OE
	BLE
								BLE
Notes

1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05445 Rev. *E		Revised May 07, 2007

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