Cypress CY14B104NA, CY14B104LA manual Features, Functional Description, Logic Block Diagram1, 2

PRELIMINARY

CY14B104LA, CY14B104NA

4 Mbit (512K x 8/256K x 16) nvSRAM

Features

■20 ns, 25 ns, and 45 ns access times

■Internally organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA)

■Hands off automatic STORE on power down with only a small capacitor

■STORE to QuantumTrap® nonvolatile elements initiated by software, device pin, or AutoStore® on power down

■RECALL to SRAM initiated by software or power up

■Infinite Read, Write, and Recall cycles

■200,000 STORE cycles to QuantumTrap

■20 year data retention

■Single 3V +20%, -10%operation

■Commercial and industrial temperatures

■48-ball FBGA and 44/54-pin TSOP-II packages

■Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104LA/CY14B104NA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

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Notes

1.Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration.

2.Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.

3.BHE and BLE are applicable for x16 configuration only.

Cypress Semiconductor Corporation • 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-49918 Rev. *A		Revised March 11, 2009

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