Cypress CY14B104LA, CY14B104NA manual AC Switching Characteristics, Switching Waveforms

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PRELIMINARY

CY14B104LA, CY14B104NA

AC Switching Characteristics

 

Parameters

Description

20 ns

25 ns

45 ns

Unit

 

Cypress

 

Alt

Min

Max

Min

Max

Min

Max

 

Parameters

 

Parameters

 

 

 

 

 

 

 

 

 

 

 

 

SRAM Read Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tACE

tACS

Chip Enable Access Time

 

20

 

25

 

45

ns

tRC[13]

tRC

Read Cycle Time

20

 

25

 

45

 

ns

t

[14]

t

AA

Address Access Time

 

20

 

25

 

45

ns

 

AA

 

 

 

 

 

 

 

 

 

tDOE

tOE

Output Enable to Data Valid

 

10

 

12

 

20

ns

tOHA[14]

tOH

Output Hold After Address Change

3

 

3

 

3

 

ns

tLZCE[12, 15]

tLZ

Chip Enable to Output Active

3

 

3

 

3

 

ns

tHZCE[12, 15]

tHZ

Chip Disable to Output Inactive

 

8

 

10

 

15

ns

tLZOE[12, 15]

tOLZ

Output Enable to Output Active

0

 

0

 

0

 

ns

tHZOE[12, 15]

tOHZ

Output Disable to Output Inactive

 

8

 

10

 

15

ns

tPU[12]

tPA

Chip Enable to Power Active

0

 

0

 

0

 

ns

tPD[12]

tPS

Chip Disable to Power Standby

 

20

 

25

 

45

ns

tDBE

-

Byte Enable to Data Valid

 

10

 

12

 

20

ns

tLZBE[12]

-

Byte Enable to Output Active

0

 

0

 

0

 

ns

tHZBE[12]

-

Byte Disable to Output Inactive

 

8

 

10

 

15

ns

SRAM Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWC

tWC

Write Cycle Time

20

 

25

 

45

 

ns

tPWE

tWP

Write Pulse Width

15

 

20

 

30

 

ns

tSCE

tCW

Chip Enable To End of Write

15

 

20

 

30

 

ns

tSD

tDW

Data Setup to End of Write

8

 

10

 

15

 

ns

tHD

tDH

Data Hold After End of Write

0

 

0

 

0

 

ns

tAW

tAW

Address Setup to End of Write

15

 

20

 

30

 

ns

tSA

tAS

Address Setup to Start of Write

0

 

0

 

0

 

ns

tHA

tWR

Address Hold After End of Write

0

 

0

 

0

 

ns

tHZWE[12, 15,16]

tWZ

Write Enable to Output Disable

 

8

 

10

 

15

ns

tLZWE[12, 15]

tOW

Output Active after End of Write

3

 

3

 

3

 

ns

tBW

-

Byte Enable to End of Write

15

 

20

 

30

 

ns

Switching Waveforms

Figure 6. SRAM Read Cycle #1: Address Controlled[13, 14, 17]

 

tRC

Address

Address Valid

 

tAA

Data Output

Previous Data Valid

 

tOHA

Notes

13.WE must be HIGH during SRAM read cycles.

14.Device is continuously selected with CE, OE and BHE / BLE LOW.

15.Measured ±200 mV from steady state output voltage.

16.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

17.HSB must remain HIGH during read and write cycles.

Output Data Valid

Document #: 001-49918 Rev. *A

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Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor Corporation 198 Champion CourtX16 Top View Not to scale PinoutsTsop Pin Definitions Sram Write Device OperationSram Read AutoStore OperationA15 A07 Mode Power Hardware Recall Power UpMode Selection Software StoreData Protection Mode Selection A15 A07 PowerPreventing AutoStore Noise ConsiderationsBest Practices Operating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsAC Switching Characteristics Switching WaveformsBHE, BLE Input Data Valid High Impedance Data Input Data OutputData Input Input Data Valid High Impedance Data Output Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallHSB Software Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthTruth Table For Sram Operations Inputs/Outputs2 Mode PowerHSB should remain High for Sram Operations Ordering Information CY14B104LA-ZS45XIT CY14B104LA-ZS45XCTCY14B104LA-ZS45XC CY14B104LA-ZS45XIZS Tsop Part Numbering NomenclatureCY 14 B 104 L a -ZS P 20 X C T NvsramPackage Diagrams TOP ViewBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Sales, Solutions, and Legal InformationDocument History USB