Cypress CY14B104LA, CY14B104NA manual Package Diagrams, TOP View

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PRELIMINARY

CY14B104LA, CY14B104NA

Package Diagrams

DIMENSION IN MM (INCH)

MAX

MIN.

O R E

K X A

S G

EJECTOR PIN

0° -5°

0.10 (.004)

18.517 (0.729)

18.313 (0.721)

10.262 (0.404)

10.058 (0.396)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

51-85087-*A

Document #: 001-49918 Rev. *A

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor Corporation 198 Champion CourtTsop PinoutsX16 Top View Not to scale Pin Definitions Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A07 Mode Power Software StoreMode Selection A15 A07 Power Preventing AutoStoreData Protection Noise ConsiderationsBest Practices DC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsBHE, BLE Data Input Input Data Valid High Impedance Data Output Data Input Data OutputInput Data Valid High Impedance HSB AutoStore/Power Up RecallParameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthHSB should remain High for Sram Operations Inputs/Outputs2 Mode PowerTruth Table For Sram Operations Ordering Information CY14B104LA-ZS45XCT CY14B104LA-ZS45XCCY14B104LA-ZS45XIT CY14B104LA-ZS45XIPart Numbering Nomenclature CY 14 B 104 L a -ZS P 20 X C TZS Tsop NvsramPackage Diagrams TOP ViewBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Sales, Solutions, and Legal Information Document HistoryGVCH/PYRS USB