Cypress CY14B104NA, CY14B104LA manual Bhe, Ble

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PRELIMINARY

CY14B104LA, CY14B104NA

Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 13, 17]

Address

Address Valid

Note

18. CE or WE must be >VIH during address transitions.

Document #: 001-49918 Rev. *A

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram1, 2 Functional DescriptionTsop PinoutsX16 Top View Not to scale Pin Definitions AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A07 Mode PowerNoise Considerations Mode Selection A15 A07 PowerPreventing AutoStore Data ProtectionBest Practices Range DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSwitching Waveforms AC Switching CharacteristicsBHE, BLE Data Input Input Data Valid High Impedance Data Output Data Input Data OutputInput Data Valid High Impedance HSB AutoStore/Power Up RecallParameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min MaxHSB should remain High for Sram Operations Inputs/Outputs2 Mode PowerTruth Table For Sram Operations Ordering Information CY14B104LA-ZS45XI CY14B104LA-ZS45XCTCY14B104LA-ZS45XC CY14B104LA-ZS45XITNvsram Part Numbering NomenclatureCY 14 B 104 L a -ZS P 20 X C T ZS TsopTOP View Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 USB Sales, Solutions, and Legal InformationDocument History GVCH/PYRS