Cypress CY14B104LA, CY14B104NA manual Data Input Data Output, Input Data Valid High Impedance

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PRELIMINARY

CY14B104LA, CY14B104NA

Figure 9. SRAM Write Cycle #2: CE Controlled[3, 16, 17, 18]

Address

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 16, 17, 18]
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Document #: 001-49918 Rev. *A

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor Corporation 198 Champion CourtPinouts X16 Top View Not to scaleTsop Pin Definitions Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A07 Mode Power Software StoreMode Selection A15 A07 Power Preventing AutoStoreData Protection Noise ConsiderationsBest Practices DC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsBHE, BLE Data Input Data Output Input Data Valid High ImpedanceData Input Input Data Valid High Impedance Data Output AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxHSB Software Controlled STORE/RECALL Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthInputs/Outputs2 Mode Power Truth Table For Sram OperationsHSB should remain High for Sram Operations Ordering Information CY14B104LA-ZS45XCT CY14B104LA-ZS45XCCY14B104LA-ZS45XIT CY14B104LA-ZS45XIPart Numbering Nomenclature CY 14 B 104 L a -ZS P 20 X C TZS Tsop NvsramPackage Diagrams TOP ViewBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Sales, Solutions, and Legal Information Document HistoryGVCH/PYRS USB