Cypress CY14B104LA, CY14B104NA manual Pinouts, X16 Top View Not to scale, Tsop

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PRELIMINARY

CY14B104LA, CY14B104NA

Pinouts

Figure 1. Pin Diagram - 48 FBGA

(x8)

Top View (not to scale)

1

2

 

3

4

5

6

 

NC

OE

 

A0

A1

A2

NC

A

NC

NC

 

A3

A4

CE

NC

B

DQ0

NC

 

A5

A6

NC

DQ4

C

VSS

DQ

 

A

A7

DQ

VCC

D

 

1

17

 

5

 

 

VCC

DQ

2

V

A16

DQ

VSS

E

 

 

CAP

 

6

 

 

DQ3

NC

 

A14

A15

NC

DQ7

F

NC[5]

HSB

A12

A13

WE

NC

G

A18

A8

 

A9

A10

A11

NC [4]

H

(x16)

Top View

(not to scale)

1

2

3

4

5

6

 

BLE

OE

A0

A1

A2

NC

A

DQ8

BHE

A

A

CE

DQ

B

 

 

3

4

 

0

 

DQ9

DQ10

A5

A6

DQ1

DQ2

C

VSS

DQ

A

A7

DQ

VCC

D

 

11

17

 

3

 

 

VCC

DQ

V

A16

DQ

VSS

E

 

12

CAP

 

4

 

 

DQ14

DQ13

A14

A15

DQ5

DQ6

F

DQ15

HSB

A12

A13

WE

DQ7

G

NC[4]

A

A

A

A

[5]

H

 

8

9

10

11

NC

Figure 2. Pin Diagram - 44 Pin TSOP II

(x8)

(x16)[6]

NC

NC[5]

A0

A1

A2

A3

A4

CE

DQ0

DQ1

VCC

VSS

DQ2

DQ3

WE A5 A6 A7 A8 A9

NC

NC

1

2

3

4

5

6

7

8

944 - TSOP II

10(x8)

11

12Top View

13(not to scale)

14

15

16

17

18

19

20

21

22

44 HSB

43 NC

42 NC[4]

41 A18

40 A17

39 A16

38 A15

37 OE

36 DQ7

35 DQ6

34 VSS

33 VCC

32 DQ5

31 DQ4

30 VCAP

29 A14

28 A13

27 A12

26 A11

25 A10

24 NC

23 NC

 

 

A0

 

 

1

 

 

 

 

 

 

 

 

A1

 

 

2

 

 

 

 

 

 

 

 

A2

 

 

3

 

 

 

 

 

 

 

 

A3

 

 

4

 

 

 

 

 

 

 

 

A4

 

 

5

 

 

 

 

 

 

 

 

CE

 

 

 

6

 

 

 

 

DQ0

 

 

7

 

 

 

 

 

 

DQ1

 

 

8

44 - TSOP II

 

 

 

DQ2

 

 

9

 

 

DQ3

 

 

 

 

10

(x16)

 

 

 

 

 

 

 

 

VCC

 

 

11

Top View

 

 

 

VSS

 

 

12

 

 

DQ

 

 

13

(not to scale)

 

4

 

 

 

 

 

 

 

 

 

 

DQ5

 

 

14

 

 

 

 

 

 

 

DQ6

 

 

 

15

 

 

 

 

 

 

 

 

 

DQ7

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

17

 

 

WE

 

 

 

 

 

 

 

 

 

 

A5

 

 

 

18

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

19

 

 

 

 

 

 

 

A7

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

A8

 

 

21

 

 

 

 

 

 

 

 

 

A9

 

 

22

 

 

 

 

 

 

 

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A17

A16

A15

OE

BHE

BLE

DQ15

DQ14

DQ13

DQ12

VSS VCC

DQ11

DQ10

DQ9

DQ8

VCAP

A14

A13

A12

A11

A10

Notes

4.Address expansion for 8 Mbit. NC pin not connected to die.

5.Address expansion for 16 Mbit. NC pin not connected to die.

6.HSB pin is not available in 44-TSOP II (x16) package.

Document #: 001-49918 Rev. *A

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Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor Corporation 198 Champion CourtTsop PinoutsX16 Top View Not to scale Pin Definitions Sram Write Device OperationSram Read AutoStore OperationA15 A07 Mode Power Hardware Recall Power UpMode Selection Software StoreData Protection Mode Selection A15 A07 PowerPreventing AutoStore Noise ConsiderationsBest Practices Operating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsAC Switching Characteristics Switching WaveformsBHE, BLE Data Input Input Data Valid High Impedance Data Output Data Input Data OutputInput Data Valid High Impedance HSB AutoStore/Power Up RecallParameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthHSB should remain High for Sram Operations Inputs/Outputs2 Mode PowerTruth Table For Sram Operations Ordering Information CY14B104LA-ZS45XIT CY14B104LA-ZS45XCTCY14B104LA-ZS45XC CY14B104LA-ZS45XIZS Tsop Part Numbering NomenclatureCY 14 B 104 L a -ZS P 20 X C T NvsramPackage Diagrams TOP ViewBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Sales, Solutions, and Legal InformationDocument History USB