Cypress CY14B104NA, CY14B104LA manual Best Practices

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PRELIMINARY

CY14B104LA, CY14B104NA

Best Practices

nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:

■The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufac- turing test to ensure these system routines work consistently.

■Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines.

■The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.

Document #: 001-49918 Rev. *A

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram1, 2 Functional DescriptionX16 Top View Not to scale PinoutsTsop Pin Definitions AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A07 Mode PowerNoise Considerations Mode Selection A15 A07 PowerPreventing AutoStore Data ProtectionBest Practices Range DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSwitching Waveforms AC Switching CharacteristicsBHE, BLE Input Data Valid High Impedance Data Input Data OutputData Input Input Data Valid High Impedance Data Output Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallHSB Software Controlled STORE/RECALL Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min MaxTruth Table For Sram Operations Inputs/Outputs2 Mode PowerHSB should remain High for Sram Operations Ordering Information CY14B104LA-ZS45XI CY14B104LA-ZS45XCTCY14B104LA-ZS45XC CY14B104LA-ZS45XITNvsram Part Numbering NomenclatureCY 14 B 104 L a -ZS P 20 X C T ZS TsopTOP View Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 USB Sales, Solutions, and Legal InformationDocument History GVCH/PYRS
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