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Board Level Hardware Description
3.Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16, or 32 bits. Reads to the LCSR and GCSR may be 8, 16, or 32 bits.
4.This area does not return an acknowledge signal. If the processor bus timeout timer is enabled, the access times out and is terminated by a TEA signal.
5.Size is approximate.
6.Port commands to the 82596CA must be written as two
7.DROM (BOOT ROM) appears at $0 following a local peripheral bus reset. The DROM appears at 0 until the DR0 bit is cleared in the PCCchip2. The DR0 bit is located at address 0 bit D15. The DROM must be disabled at 0 before the DRAM is accessed.
VMEbus Memory Map
This section describes the mapping of local resources as viewed by VMEbus masters.
VMEbus Accesses to the Local Peripheral Bus
The VMEchip2 includes a
VMEbus Short I/O Memory Map
The VMEchip2 includes a
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