Motorola MVME197LE manual VMEbus Memory Map, VMEbus Accesses to the Local Peripheral Bus

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Board Level Hardware Description

3.Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16, or 32 bits. Reads to the LCSR and GCSR may be 8, 16, or 32 bits.

4.This area does not return an acknowledge signal. If the processor bus timeout timer is enabled, the access times out and is terminated by a TEA signal.

5.Size is approximate.

6.Port commands to the 82596CA must be written as two 16-bit writes: upper word first and lower word second.

7.DROM (BOOT ROM) appears at $0 following a local peripheral bus reset. The DROM appears at 0 until the DR0 bit is cleared in the PCCchip2. The DR0 bit is located at address 0 bit D15. The DROM must be disabled at 0 before the DRAM is accessed.

VMEbus Memory Map

This section describes the mapping of local resources as viewed by VMEbus masters.

VMEbus Accesses to the Local Peripheral Bus

The VMEchip2 includes a user-programmable map decoder for the VMEbus to local peripheral bus interface. The map decoder allows the user to program the starting and ending address and the modifiers the MVME197LE responds to.

VMEbus Short I/O Memory Map

The VMEchip2 includes a user-programmable map decoder for the GCSR (Global Control and Status Registers). The GCSR map decoder allows the user to program the starting address of the GCSR in the VMEbus short I/O space.

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Installation Guide

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Contents MVME197LE Restricted Rights Legend Preface Document TerminologyBIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Hardware Preparation and Installation Using the 197Bug Debugger Appendix a Configure and Environment Commands List of Figures Xiv List of Tables Xvi Introduction OverviewRequirements Features MVME197LE Specifications SpecificationsBlock Diagram Block Diagram Bus Data Bus 256 BusSwitch MC88110 Address Data MUX AddressMezzanine Address Bus Memory ArrayFront Panel Switches and Indicators Functional DescriptionData Bus Structure MC88110 MPUFlash Memory Onboard DramBattery Backup RAM and Clock VMEbus InterfaceInterfaces Serial Port InterfacePrinter Interface Ethernet InterfaceScsi Interface Scsi TerminationPeripheral Resources Connectors Memory MapsInterrupt Sources Processor Bus Memory MapProcessor Bus Memory Map DramsizeAddress Range Devices Accessed Port Size Local Devices Memory MapVMEbus Short I/O Memory Map VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map Unpacking Instructions Hardware PreparationHardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Installation Instructions Switch S6MVME197LE Module Installation System Considerations MVME197LEIG/D1 Hardware Preparation and Installation Overview of M88000 Firmware Description of 197Bug197Bug Implementation Installation and Start-upComparison With M68000-Based Firmware Terminal to make sure XON/XOFF handshaking is enabled OteAutoboot ROMboot Network BootReset Restarting the SystemAbort BreakMPU Clock Speed Calculation Memory RequirementsSYSFAIL* Assertion/Negation Terminal Input/Output Control DELDevice Probe Function Disk I/O SupportBlocks Versus Sectors Disk I/O via 197Bug Commands Disk I/O via 197Bug System Calls DskcfigNetwork I/O Support Default 197Bug Controller and Device ParametersDisk I/O Error Codes Bootp Protocol Module Physical Layer Manager Ethernet DriverUDP/IP Protocol Modules RARP/ARP Protocol ModulesNetwork Boot Control Module Network I/O Error CodesMultiprocessor Support Multiprocessor Control Register Mpcr MethodMpar Diagnostic Facilities Gcsr MethodDebugger General Information Entering Debugger Command Lines DebuggerSyntactic Variables Expression as a ParameterData Type Base Identifier Examples Offset Registers Address as a ParameterAddress Formats Entering and Debugging Programs Port NumbersCalling System Utilities From User Programs Preserving The Debugger Operating Environment197Bug Vector Table and Workspace Hardware FunctionsFloating Point Support CPU/MPU RegistersScientific Notation Single Precision RealDouble Precision Real 197Bug Debugger Command Set Debugger CommandsNocm Noma Name Nioc RL Addrbhw Using the 197Bug Debugger Configure Board Information Block Cnfg MISet Environment to Bug/Operating System ENV DTable A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of DefaultConfigure and Environment Commands Ffbffffc Table A-1. ENV Command Parameters Memory Requirement s 01FFFFFF Table A-1. ENV Command Parameters Efffffff FF7FFFFF Table A-1. ENV Command Parameters Table A-1. ENV Command Parameters Table A-1. ENV Command Parameters DISK/TAPE Controller Data Disk/Tape Controller Modules SupportedDisk/Tape Controller Default Configurations Single Board Computers 7 DevicesMVME320 4 Devices MVME323 4 DevicesMVME327A 9 Devices MVME328 14 DevicesMVME350 1 Device IOT Command Parameters for Supported Floppy Types IOT ParameterDisk/Tape Controller Data Network Controller Data Network Controller Modules SupportedNetwork Controller Data Symbols NumericsIN-2 IN-3 Nvram A-2 XON/XOFF Index
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