Functional Description
DRAM is not disabled by a local peripheral bus reset. Refer to the DCAM and ECDM chapters in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.
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Battery Backup RAM and Clock
The MK48T08 RAM and clock chip is used on the MVME197LE. This chip provides a time of day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one
VMEbus Interface
The local peripheral bus to VMEbus interface, the VMEbus to local peripheral bus interface, and the
I/O Interfaces
The MVME197LE provides onboard I/O for many system applications. The I/O functions include serial ports, a printer port, an Ethernet transceiver interface, and a SCSI mass storage interface.
Serial Port Interface
The CD2401 serial controller chip (SCC) is used to implement the four serial ports. The serial ports support the standard baud rates (110 to 38.4K baud). Serial port 4 also supports synchronous modes of operation.
The four serial ports are different functionally because of the limited number of pins on the I/O connector. Serial port 1 is a minimum function asynchronous port. It uses RXD, CTS, TXD, and RTS. Serial ports 2 and 3 are full function asynchronous ports. They use RXD, CTS, DCD, TXD, RTS, and DTR. Serial port 4 is a full function asynchronous or synchronous port. It can
MVME197LEIG/D1 |