CROSSPOINTARCHITECTURE
Figure 1.5 is a simplified representation of the interface between the I/O connectors, the dynamic ports, and the crosspoint matrix. The crosspoint matrix itself consists of four LSI 64x64 crosspoint chips connected in a unidirectional 128x128 “m by n” architecture. In this non-blocking scheme, any of the 128 inputs can be switched to any of the 128 outputs. Each output is controlled by a double-buffered register with a load and an active segment. Upon receipt of an XY take command, the command interpreter fills the load segment with the address of the input port to which the output will be connected. The take is consummated when the crosspoint strobe dumps the contents of the load registers into the active registers. The entire process of mapping the switch in this fashion occurs within one video vertical retrace time.
At the crosspoint level, the NV3128 is an
For each requested machine connection, the router uses the input command information to ensure that the controlling machine automatically sees a controlled router port, and that the controlled machine looks back into a controlling port. In practice, this means that the NV3128 can dynamically implement the connections of Fig. 1 and Fig 3 in successive sessions. In Fig. 1.1, the editor controls VTR A, which is a controlled device. In a further session, VTR A dubs down to VTR B, with VTR A now a controlling device, as shown in Fig.
1.3.In a conventional routing switch, this arrangement would require physical
NV3128 |