SSI
EPS2U Power Supply Design Guide, V2.1
Vout
| V1 | 10% Vout |
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| V2 |
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| V3 |
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| V4 |
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| Tvout_rise |
| Tvout_off |
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| Tvout_on |
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| Figure 2: Output Voltage Timing |
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| Table 24: Turn On/Off Timing |
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| Description | MIN |
| MAX | UNITS |
Tsb_on_delay |
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| Delay from AC being applied to 5 VSB being |
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| 1500 | ms |
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| within regulation. |
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T ac_on_delay |
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| Delay from AC being applied to all output voltages |
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| 2500 | ms |
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| being within regulation. |
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Tvout_holdup |
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| Time all output voltages stay within regulation | 18 |
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| ms |
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| after loss of AC. |
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Tpwok_holdup |
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| Delay from loss of AC to deassertion of PWOK. | 17 |
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| ms |
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Tpson_on_delay |
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| Delay from PSON# active to output voltages within | 5 |
| 400 | ms |
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| regulation limits. |
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T pson_pwok |
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| Delay from PSON# deactive to PWOK being |
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| 50 | ms |
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| deasserted. |
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Tpwok_on |
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| Delay from output voltages within regulation limits | 100 |
| 1000 | ms |
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| to PWOK asserted at turn on. |
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T pwok_off |
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| Delay from PWOK deasserted to output voltages | 1 |
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| ms |
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| (3.3 V, 5 V, 12 V, |
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| limits. |
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Tpwok_low |
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| Duration of PWOK being in the deasserted state | 100 |
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| ms |
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| during an off/on cycle using AC or the PSON# |
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| signal. |
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Tsb_vout |
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| Delay from 5 VSB being in regulation to O/Ps | 50 |
| 1000 | ms |
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| being in regulation at AC turn on. |
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| - 22 - |
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