Transcend Information TS128GSSD25S-M, TS64GSSD25S-M, TS64GSSD25S-S, TS32GSSD25S-M dimensions Comreset

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TS8GSSD25S-S

 

TS16GSSD25S-S/M

 

TS32GSSD25S-S/M

 

TS64GSSD25S-S/M

 

TS128GSSD25S-M

2.5” Solid State Disk

TS192GSSD25S-M

COMRESET

COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than six data bursts, including inter-burst temporal spacing. The COMRESET signal shall be:

1)Sustained/continued uninterrupted as long as the system hard reset is asserted, or

2)Started during the system hardware reset and ended some time after the negation of system hardware reset, or

3)Transmitted immediately following the negation of the system hardware reset signal.

The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until the COMRESET signal is transmitted. Each burst shall be 160 Gen1 UI’s long (106.7 ns) and each inter-burst idle state shall be 480 Gen1 UI’s long (320 ns). A COMRESET detector looksfor four consecutive bursts with 320 ns spacing (nominal). Any spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The COMRESET interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 5 below. The interface shall be held inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly.

Transcend Information Inc.

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V1.08

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Contents Description Placement FeaturesDimensions V1.08Specifications Sequential WriteMax Model P/N Sequential ReadMaxModel P/N User Max. LBA Cylinder Head Sector Operating Non-Operating Data Reliability Data RetentionCompliance Package Dimensions Pin Layout Pin AssignmentsPin No Pin Name Block Diagram ECC algorithm ReliabilityWear-Leveling algorithm Bad-block managementOut of bank signaling Sata InterfaceComreset TS192GSSD25S-M Cominit TS192GSSD25S-M Power on sequence timing diagram Power on sequenceATA command register Command Table Command Name CodeSET Features ATA Command Specifications Identify Device Information Default Value Word Value DescriptionPIO data transfer cycle timing mode Reserved TS192GSSD25S-M Minor version number TS192GSSD25S-M TS192GSSD25S-M Current AAM value 15-8 Vendor’s recommended AAM value 95-99 Initialize Device Parameters 91h Idle E3hIdle Immediate E1h Read Buffer E4hRead Fpdma Queued 60h Log Address Log Name Feature Set AccessRead DMA EXT 25h Read LOG EXT 2FhRead Verify Sectors EXT 42h Security Disable Password F6hRead Verify Sectors 40h/41h Recalibrate 10hSecurity SET Password F1h Security set Password data contentSecurity Unlock F2h Features register Value and settable operating mode Code Smart Subcommand Smart Function Set B0hByte 2-361 Individual attribute data Byte DescriptionAttribute ID information is listed in the following table Description Detail Information ByteSmart Read Attribute Threshold Smart Enabl Operations Write Buffer E8h Standby E2hStandby Immediate E0h Write DMA CAhWrite Sectors 30h/31h Write Multiple EXT 39hWrite Multiple FUA EXT CEh Write Sectors EXT 34hOrdering Information Taiwan Germany
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