Transcend Information TS32GSSD25S-S, TS128GSSD25S-M, TS64GSSD25S-M dimensions ATA command register

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TS8GSSD25S-S

 

TS16GSSD25S-S/M

 

TS32GSSD25S-S/M

 

TS64GSSD25S-S/M

 

TS128GSSD25S-M

2.5” Solid State Disk

TS192GSSD25S-M

Description:

1.Host/device power-off - Host and device power-off.

2.Power is applied - Host side signal conditioning pulls TX and RX pairs to neutral state (common mode voltage).

3.Host issues COMRESET

4.Host releases COMRESET. Once the power-on reset is released, the host releases the COMRESET signal and puts the bus in a quiescent condition.

5.Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT.

6.Host calibrates and issues a COMWAKE.

7.Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP primitives have been sent for 54.6 us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP primitives at that rate for 54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached without response from the host, the device shall enter an error state.

8.Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This insures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer.

9.Device locks – the device locks to the ALIGN sequence and, when ready, sends the SYNCP primitive indicating it is ready to start normal operation.

10.Upon receipt of three back-to-back non-ALIGNPprimitives, the communication link is established and normal operation may begin.

ATA command register

This table with the following paragraphs summarizes the ATA command set.

Transcend Information Inc.

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V1.08

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Contents V1.08 Placement FeaturesDimensions DescriptionSpecifications Model P/N Sequential ReadMax Sequential WriteMaxModel P/N User Max. LBA Cylinder Head Sector Data Reliability Data Retention Operating Non-OperatingCompliance Package Dimensions Pin Assignments Pin LayoutPin No Pin Name Block Diagram Bad-block management ReliabilityWear-Leveling algorithm ECC algorithmSata Interface Out of bank signalingComreset TS192GSSD25S-M Cominit TS192GSSD25S-M Power on sequence Power on sequence timing diagramATA command register Command Name Code Command TableSET Features ATA Command Specifications Word Value Description Identify Device Information Default ValuePIO data transfer cycle timing mode Reserved TS192GSSD25S-M Minor version number TS192GSSD25S-M TS192GSSD25S-M Current AAM value 15-8 Vendor’s recommended AAM value 95-99 Read Buffer E4h Idle E3hIdle Immediate E1h Initialize Device Parameters 91hRead LOG EXT 2Fh Log Address Log Name Feature Set AccessRead DMA EXT 25h Read Fpdma Queued 60hRecalibrate 10h Security Disable Password F6hRead Verify Sectors 40h/41h Read Verify Sectors EXT 42hSecurity set Password data content Security SET Password F1hSecurity Unlock F2h Features register Value and settable operating mode Smart Function Set B0h Code Smart SubcommandByte Description Byte 2-361 Individual attribute dataDescription Detail Information Byte Attribute ID information is listed in the following tableSmart Read Attribute Threshold Smart Enabl Operations Write DMA CAh Standby E2hStandby Immediate E0h Write Buffer E8hWrite Sectors EXT 34h Write Multiple EXT 39hWrite Multiple FUA EXT CEh Write Sectors 30h/31hTaiwan Germany Ordering Information
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