Samsung manual Spinpoint M9T Product Manual REV

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DATA CHARACTER-A data character is a combination of a byte value with the control variable equal to D.

DWORD-A Dword is thirty-two (32) bits of data. A Dword may be represented as 32 bits, as two adjacent words, or as four adjacent bytes. When shown as bits the least significant bit is bit 0 and most significant bit is bit 31. The most significant bit is shown on the left. When shown as words the least significant word (lower) is word 0 and the most significant (upper) word is word 1. When shown as bytes the least significant byte is byte 0 and the most significant byte is byte 3.

DWORD SYNCHRINIZATION-The state in which a receiver has recognized the comma sequence and is producing an aligned data stream of Dwords (four contiguous bytes) from the zero-reference of the comma character.

ENCODED CHARACTER-An encoded character is the output of the 8b/10b encoder – the result of encoding a character. An encoded character consists of 10 bits, where bit 0 is the most significant bit and bit

9 is the least significant. The bits in an encoded character are symbolically referred to as “abcdeifghj” where “a” corresponds to bit 0 and “j” corresponds to bit 9.

ELASTICITY BUFFER-The elasticity buffer is a portion of the receiver where character slipping and/or character alignment is performed.

FIRST PARTY DMA ACCESS -First-party DMA access is a method by which a device accesses host memory.

FIRST PARTY DMA MODE (FPDMA) - A device which is operating in First-party DMA mode uses First- party DMA as a primary communications method between the host and the device. A software driver uses legacy mode commands to place the device into First-party DMA mode of operation. The legacy-mode command places the device into the First-party DMA mode of operation and the command protocol used between a device and host when in First-party DMA mode are not specified by this specification.

FIRST DATA PHASE- The FPDMA Data Phase is the period from the reception of a DMA Setup FIS until either the exhaustion of the associated data transfer count or the assertion of the ERR bit in the shadow Status register.

FIS-Stands for Frame Information Structure.

FRAME UNFIORMATION STRUCTURE-The user payload of a frame, does not include the SOF, CRC, and EOF delimiters.

Frame-A frame is an indivisible unit of information exchanged between a host and device. A frame consists of a SOF primitive, a Frame Information Structure, a CRC calculated over the contents of the FIS, and an EOF primitive-

LEGACY MODE-Legacy mo d e is the mode of operation which provides software-transparent communication of commands and status between a host and device using the ATA Command Block and Control Block registers.

LEGAL CHARACTER-Legal character is one for which there exists a valid decoding, either into the data character or control character fields. Due to running disparity constraints not all 10-bit combinations result in a legal character. Additional usage restrictions in Serial ATA result in a further reduction in the SATA defined control character space.

OOB SIGNAL DETECTOR-This block decodes Out of Band signal from the high speed input signal path.

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Contents M9T Product Manual Page Table of Contents Iii Read Fpdma Queued 60h Read Log Extended 2Fh Read Long 22h Table of Tables User Definition ScopeManual Organization Sata ReferenceDescription IntroductionKey Features Standards and Regulations Hardware RequirementsSpecifications Specification SummaryPhysical Specifications Logical ConfigurationsPerformance Specifications Power consumption Power consumptionPower Requirements RatedEnvironmental Specifications Environmental SpecificationsLinear Shock 1/2 sine pulse Rotational ShockReliability Specifications Installation Space RequirementsUnpacking Instructions MountingMounting Dimensions OrientationVentilation Cable ConnectorsSata Connectivity Computer mainboard or Serial ATA host adapter Power ManagementSATA-Bus Interface Connector HDD Power, Sata Interface, and Factory Jumper ConnectorDrive Installation DC Power Connector and SATA-Bus Interface Cable ConnectionsHead / Disk Assembly HDA Base Casting AssemblyDC Spindle Motor Assembly Disk Drive OperationExploded Mechanical View Disk Stack Assembly Head Stack AssemblyVoice Coil Motor and Actuator Latch Assemblies Air Filtration SystemDrive Electronics Digital Signal Process and Interface ControllerDisk Controller DDR Host Interface Control Block Buffer Control BlockDisk Ldpc Control Block Disk Control BlockFrequency Synthesizer Power Management Read/Write ICTime Base Generator Automatic Gain ControlAnalog Anti-Aliasing Low Pass Filter Analog to Digital Converter ADC and FIRRead and Write Operations Servo SystemRead Channel Write Channel Firmware FeaturesRead Caching Write Caching Defect Management Automatic Defect AllocationSmart 6 APMSata II Interface Sata TerminologySpinpoint M9T Product Manual REV Physical Interface Signal Summary Signal DescriptionsWhen read When written 2 I/O Register AddressControl Block Register Descriptions RegistersCommand Block Register Descriptions Command Register Ex F7h Device Register Ex F6hStatus Register Ex F7h Sata II Feature SET Device Activity SignalStaggered Spin-up Disable Control Auto-Activate in DMA Setup FISPhy Event Counters Software Settings Preservation Sata Power ManagementCommand Table ATA Command DescriptionsCommand Code Parameters Smart Command Descriptions Check Power Mode E5hDevice Configuration Overlay B1h Download Micro Code 92hDevice Configuration Identify data structure Word Content Execute Device Diagnostics 90h Diagnostic CodesFlush Cache E7h, EAh extended Format Track 50hContent Description Identify Device information=the fields reported in word 88 are valid EXT =Media Card Pass Through command feature set supported Word Content Description WWNIdle E3h Automatic Standby Timer PeriodsIdle Immediate E1h Initialize Device Parameters 91h NOP 00hRead Buffer E4h Read DMA C8h, 25h extendedRead Log Extended 2Fh Read Multiple Command C4h, 29h extendedRead Long 22h Read Sectors 20h, 24h extended Read Native Max Address F8h, 27h extendedRead Verify Sectors 40h, 41h extended Security Disable Password F6h Recalibrate 10hSecurity Erase Prepare F3h Security Erase Unit F4hSecurity Set Password F1h Security Erase Unit Password Word ContentSecurity Set Password data content Security Freeze Lock F5hSecurity Unlock F2h Set Features EFhSeek 7xh 11 Set Features Register Definitions 12 Transfer Mode ValuesSet Multiple Mode C6h 13 Set Max Feature Register ValuesSet Max Address F9h, 37h extended Sleep E6h14 Smart Feature Registers Values Smart disable operations D9hSmart enable/disable attribute auto-save D2h Smart B0hSmart enable operations D8h Smart execute off-line immediate D4hSmart read data D0h 15 Device Smart Data StructureByte Bit Name Description 16 Smart Attribute Status Flags17 Smart Attribute Data List 18 Off-line Data Collection Status ValuesSelf-test execution status byte 19 Self-test Execution Status ValuesSmart return status DAh Smart read log sector D5hSmart write log sector D6h Standby Immediate E0h Write Buffer E8hWrite DMA CAh, 35h extended Write Fpdma Queued 61hWrite Multiple Command C5h, 39h extended Write Sectors 30h, 34h extendedSpinpoint M9T Product Manual REV Maintenance Precautions MaintenanceGeneral Information HDD handling guide -Please handle HDD by side surfaces Service and Repair HDD handling guide Prevent Shocks