Sony MDS-JE530 service manual 59, •BD BOARD IC121 CXD2656R

Page 47
•BD BOARD IC121 CXD2656R

•BD BOARD IC121 CXD2656R

(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)

Pin No.

Pin Name

I/O

 

Description

 

 

 

 

 

 

 

 

1

MNT0 (FOK)

O

Focus OK signal output to the system controller (IC501)

 

“H” is output when focus is on (“L”: NG)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

MNT1 (SHOCK)

O

Track jump detection signal output to the system controller (IC501)

 

 

 

 

 

 

 

3

MNT2 (XBUSY)

O

Busy monitor signal output to the system controller (IC501)

 

 

 

 

 

 

 

4

MNT3 (SLOCK)

O

Spindle servo lock status monitor signal output to the system controller (IC501)

 

 

 

 

 

 

5

SWDT

I

Writing serial data signal input from the system controller (IC501)

6

 

SCLK

I (S)

Serial data transfer clock signal input from the system controller (IC501)

7

 

XLAT

I (S)

Serial data latch pulse signal input from the system controller (IC501)

8

 

SRDT

O (3)

Reading serial data signal output to the system controller (IC501)

 

 

 

 

 

 

9

 

SENS

O (3)

Internal status (SENSE) output to the system controller (IC501)

 

 

 

 

 

 

 

10

 

XRST

I (S)

Reset signal input from the system controller (IC501)

“L”: reset

 

 

 

 

 

 

11

 

SQSY

O

Subcode Q sync (SCOR) output to the system controller (IC501)

 

“L” is output every 13.3 msec

Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

 

12

DQSY

O

Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC501)

“L” is output every 13.3 msec

Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

RECP

I

Laser power selection signal input from the system controller (IC501)

 

“L”: playback mode, “H”: recording mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

XINT

O

Interrupt status output to the system controller (IC501)

 

 

 

 

 

 

 

15

 

TX

I

Recording data output enable signal input from the system controller (IC501)

 

Writing data transmission timing input (Also serves as the magnetic head on/off output)

 

 

 

 

 

 

 

 

 

 

 

16

 

OSCI

I

System clock signal (512Fs=22.5792 MHz) input terminal

 

 

 

 

 

 

17

OSCO

O

System clock signal (512Fs=22.5792 MHz) output terminal

Not used (open)

18

 

XTSL

I

Input terminal for the system clock frequency setting

 

 

 

“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)

 

 

 

 

 

 

 

 

 

 

19

 

DIN0

I

Digital audio signal input terminal when recording mode (for digital optical input)

 

 

 

 

 

 

20

 

DIN1

I

Digital audio signal input terminal when recording mode (for digital optical input or digital

 

coaxial input)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

DOUT

O

Digital audio signal output terminal when playback mode (for digital optical output)

 

 

 

 

 

 

22

DATAI

I

Serial data input terminal Not used (fixed at “L”)

 

 

23

LRCKI

I

L/R sampling clock signal (44.1 kHz) input terminal

Not used (fixed at “L”)

24

XBCKI

I

Bit clock signal (2.8224 MHz) input terminal

Not used (fixed at “L”)

25

ADDT

I

Recording data input from the A/D, D/A converter (IC321)

 

 

 

 

 

 

26

DADT

O

Playback data output to the A/D, D/A converter (IC321)

 

 

 

 

 

27

LRCK

O

L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC321)

 

 

 

 

28

XBCK

O

Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC321)

 

 

 

 

 

 

29

 

FS256

O

Clock signal (11.2896 MHz) output terminal

Not used (open)

30

DVDD

—

Power supply terminal (+3.3V) (digital system)

 

 

31 to 34

A03 to A00

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

35

 

A10

O

Address signal output to the external D-RAM

Not used (open)

 

 

 

 

 

 

 

36 to 40

A04 to A08

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

41

 

A11

O

Address signal output to the external D-RAM

Not used (open)

 

 

 

 

 

 

 

 

 

42

 

DVSS

—

Ground terminal (digital system)

 

 

 

 

43

 

XOE

 

O

Output enable signal output to the D-RAM (IC124)

“L” active

44

XCAS

O

Column address strobe signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

 

 

 

* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 59 –

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Page 46 Page 48
Contents MDS-JE530 SPECIFICATIONSSERVICE MANUAL Supplied accessories– 2 – SELF-DIAGNOSISFUNCTIONSelecting the Test Mode Items of Error History Mode Items and ContentsTable of Error Codes – 3 –ELECTRICAL ADJUSTMENTS TABLE OF CONTENTS6.DIAGRAMS DISASSEMBLYADVARSEL Flexible Circuit Board RepairingNotes on chip component replacement – 5 –JIG FOR CHECKING BD BOARD WAVEFORM – 6 –Display Precedure – 7 –Record Precedure – 8 – CHECKS PRIOR TO PARTS REPLACEMENT AND ADJUSTMENTSFig. 1 Reading the Test Mode Display – 9 –RETRY CAUSE DISPLAY MODE PrecedureReading the Display – 10 –Hexadecimal nBinary Conversion Table This section is extracted from instruction manual SECTION GENERAL– 11 – LOCATION OF CONTROLSPage FRONT PANEL SECTION SECTION DISASSEMBLY– 13 – CASEMECHANISM DECK SECTTION MDM-5D – 14 –MAIN BOARD BASE UNIT MBU-5D,BD BOARD – 15 –SLIDER CAM SW BOARD, LOADING MOTOR M103 – 16 –– 17 – 1. PRECAUTIONS FOR USE OF TEST MODE2. SETTING THE TEST MODE SECTION TEST MODE5. SELECTING THE TEST MODE – 18 –5-3. Non-VolatileMemory Mode EEP MODE – 19 –5-1.Operating the Continuous Playback Mode 7. TEST MODE DISPLAYS – 20 –6. FUNCTIONS OF OTHER BUTTONS MEANINGS OF OTHER DISPLAYS – 21 –– 22 – SECTION ELECTRICAL ADJUSTMENTS1.PARTS REPLACEMENT AND ADJUSTMENT – 23 – 2. PRECAUTIONS FOR CHECKING LASER DIODE EMISSION4. PRECAUTIONS FOR ADJUSTMENTS Laser power meter– 24 – Checking Procedure6-2.Laser Power Check Specification6-4.Focus Bias Check 6-5.C PLAY Checking MO Error Rate CheckCD Error Rate Check – 25 –Setting Procedure 7. INITIAL SETTING OF ADJUSTMENT VALUE9. TEMPERATURE COMPENSATION OFFSET ADJUSTMENT 10. LASER POWER ADJUSTMENTAdjusting Procedure 11. TRAVERSE ADJUSTMENT– 27 – SpecificationAdjusting Procedure 12.FOCUS BIAS ADJUSTMENT– 28 – 13-2.MO Error Rate Check 13.ERROR RATE CHECK15.AUTO GAIN CONTROL OUTPUT LEVEL ADJUSTMENT 13-1.CD Error Rate Check– BD BOARDSide B – Adjustment Location– 30 – – BD BOARDSide A –– 32 – MDS-JE530 SECTION DIAGRAMS6-1.BLOCK DIAGRAM – MD SERVO Section – – 31 –– 34 – 6-2.BLOCK DIAGRAM – MAIN Section –MDS-JE530 – 33 –Note on Schematic Diagram – 35 –Note on Printed Wiring Board • Circuit Boards Location – 36 –•Semiconductor Location 6-4.PRINTED WIRING BOARD – BD Board –– 38 – •See page 36 for Circuit Boards LocationMDS-JE530 – 39 –– 40 – MDS-JE530 6-6.SCHEMATIC DIAGRAM – BD Board 2/2 – See•– 41 – – 42 –– 44 – 6-7.SCHEMATIC DIAGRAM – SW Board –6-8.PRINTED WIRING BOARD – SW Board – – 43 –page 36 for Circuit Boards Location 6-9.PRINTED WIRING BOARD – MAIN Board – See•– 45 – – 46 –Page Page 41 Page – 47 –– 48 – MDS-JE530MDS-JE530 – 49 –– 50 – • Semiconductor Location – 51 –– 52 – MDS-JE530Page 47 Page – 53 –– 54 – MDS-JE530IC101 •IC Block Diagrams – BD Board –– 55 – – 56 –IC431 – 57 –IC310 M5293L6-14.IC PIN FUNCTION DESCRIPTION – 58 –•BD BOARD IC121 CXD2656R – 59 –– 60 – – 61 – •MAIN BOARD IC501 M30624MG-207FPSYSTEM CONTROLLER – 62 –– 63 – – 64 – 1CHASSIS SECTION SECTION EXPLODED VIEWS– 65 – 59 54 52 2FRONT PANEL SECTION 61 64 61 63 6166 61 61 51 53223 207 – 67 –3MECHANISM SECTION MDM-5D 213 207 202 201254 253 – 68 –4BASE UNIT SECTION MBU-5D 252 263 270– 69 – SECTION ELECTRICAL PARTS LIST– 70 – DISPLAYDISPLAY KEY SW– 71 – KEY SW MAIN– 72 – MAIN – 73 –MAIN – 74 –MAIN POWER SW– 75 – 9-928-824-11 MDS-JE530– 76 – Sony Corporation
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