Sony MDS-JE530 service manual 60

Page 48
– 60 –

Pin No.

Pin Name

I/O

Description

 

 

 

 

 

 

 

 

 

45

 

A09

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

46

 

XRAS

O

Row address strobe signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

47

 

XWE

O

Write enable signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

 

48

 

D1

I/O

 

 

 

49

 

D0

I/O

Two-way data bus with the D-RAM (IC124)

 

 

50

 

D2

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

51

 

D3

I/O

 

 

 

 

 

 

 

 

 

52

 

MVCI

I (S)

Digital in PLL oscillation input from the external VCO

Not used (fixed at “L”)

 

 

 

 

 

 

 

53

 

ASYO

O

Playback EFM full-swing output terminal

 

 

 

 

 

 

 

54

 

ASYI

I (A)

Playback EFM asymmetry comparator voltage input terminal

55

 

AVDD

—

Power supply terminal (+3.3V) (analog system)

 

 

56

 

BIAS

I (A)

Playback EFM asymmetry circuit constant current input terminal

 

 

 

 

 

57

 

RFI

I (A)

Playback EFM RF signal input from the CXA2523AR (IC101)

 

 

 

 

 

 

 

58

 

AVSS

—

Ground terminal (analog system)

 

 

 

 

 

 

 

59

 

PCO

O (3)

Phase comparison output for master clock of the recording/playback EFM master PLL

 

 

 

 

 

60

 

FILI

I (A)

Filter input for master clock of the recording/playback master PLL

61

 

FILO

O (A)

Filter output for master clock of the recording/playback master PLL

62

 

CLTV

I (A)

Internal VCO control voltage input of the recording/playback master PLL

 

 

 

 

 

63

 

PEAK

I (A)

Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)

 

 

 

 

 

64

 

BOTM

I (A)

Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)

 

 

 

 

 

65

 

ABCD

I (A)

Light amount signal (ABCD) input from the CXA2523AR (IC101)

 

 

 

 

 

 

66

 

FE

I (A)

Focus error signal input from the CXA2523AR (IC101)

 

67

 

AUX1

I (A)

Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR (IC101)

68

 

VC

I (A)

Middle point voltage (+1.65V) input from the CXA2523AR (IC101)

69

 

ADIO

O (A)

Monitor output of the A/D converter input signal

Not used (open)

 

 

 

 

 

 

 

70

 

AVDD

—

Power supply terminal (+3.3V) (analog system)

 

 

 

 

 

 

 

71

 

ADRT

I (A)

A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)

 

 

 

 

 

72

 

ADRB

I (A)

A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)

73

 

AVSS

—

Ground terminal (analog system)

 

 

74

 

SE

I (A)

Sled error signal input from the CXA2523AR (IC101)

 

75

 

TE

I (A)

Tracking error signal input from the CXA2523AR (IC101)

 

 

 

 

 

 

 

76

 

DCHG

I (A)

Connected to the +3.3V power supply

 

 

 

 

 

 

 

 

77

 

APC

I (A)

Error signal input for the laser automatic power control

Not used (fixed at “H”)

 

 

 

 

 

78

 

ADFG

I (S)

ADIP duplex FM signal (22.05 kHz ± 1 kHz) input from the CXA2523AR (IC101)

 

 

 

 

 

79

 

F0CNT

O

Filter f0 control signal output to the CXA2523AR (IC101)

80

 

XLRF

O

Serial data latch pulse signal output to the CXA2523AR (IC101)

81

 

CKRF

O

Serial data transfer clock signal output to the CXA2523AR (IC101)

 

 

 

 

 

 

82

 

DTRF

O

Writing serial data output to the CXA2523AR (IC101)

 

 

 

 

 

 

 

83

 

APCREF

O

Control signal output to the reference voltage generator circuit for the laser automatic power

 

control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

84

 

LDDR

O

PWM signal output for the laser automatic power control

Not used (open)

 

 

 

 

 

85

 

TRDR

O

Tracking servo drive PWM signal (–) output to the BH6511FS (IC152)

86

 

TFDR

O

Tracking servo drive PWM signal (+) output to the BH6511FS (IC152)

87

 

DVDD

—

Power supply terminal (+3.3V) (digital system)

 

 

 

 

 

 

 

88

 

FFDR

O

Focus servo drive PWM signal (+) output to the BH6511FS (IC152)

 

 

 

 

 

89

 

FRDR

O

Focus servo drive PWM signal (–) output to the BH6511FS (IC152)

 

 

 

 

 

 

 

 

* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 60 –

Page 47 Page 49
Image 48
Page 47 Page 49
Contents SPECIFICATIONS SERVICE MANUALSupplied accessories MDS-JE530SELF-DIAGNOSISFUNCTION – 2 –Items of Error History Mode Items and Contents Table of Error Codes– 3 – Selecting the Test ModeTABLE OF CONTENTS 6.DIAGRAMSDISASSEMBLY ELECTRICAL ADJUSTMENTSFlexible Circuit Board Repairing Notes on chip component replacement– 5 – ADVARSEL– 6 – JIG FOR CHECKING BD BOARD WAVEFORM– 7 – Record PrecedureDisplay Precedure CHECKS PRIOR TO PARTS REPLACEMENT AND ADJUSTMENTS – 8 –– 9 – RETRY CAUSE DISPLAY MODEPrecedure Fig. 1 Reading the Test Mode Display– 10 – Hexadecimal nBinary Conversion TableReading the Display SECTION GENERAL – 11 –LOCATION OF CONTROLS This section is extracted from instruction manualPage SECTION DISASSEMBLY – 13 –CASE FRONT PANEL SECTION– 14 – MAIN BOARDMECHANISM DECK SECTTION MDM-5D – 15 – SLIDER CAMBASE UNIT MBU-5D,BD BOARD – 16 – SW BOARD, LOADING MOTOR M1031. PRECAUTIONS FOR USE OF TEST MODE 2. SETTING THE TEST MODESECTION TEST MODE – 17 –– 18 – 5. SELECTING THE TEST MODE– 19 – 5-1.Operating the Continuous Playback Mode5-3. Non-VolatileMemory Mode EEP MODE – 20 – 6. FUNCTIONS OF OTHER BUTTONS7. TEST MODE DISPLAYS – 21 – MEANINGS OF OTHER DISPLAYSSECTION ELECTRICAL ADJUSTMENTS 1.PARTS REPLACEMENT AND ADJUSTMENT– 22 – 2. PRECAUTIONS FOR CHECKING LASER DIODE EMISSION 4. PRECAUTIONS FOR ADJUSTMENTSLaser power meter – 23 –Checking Procedure 6-2.Laser Power CheckSpecification – 24 –6-5.C PLAY Checking MO Error Rate Check CD Error Rate Check– 25 – 6-4.Focus Bias Check7. INITIAL SETTING OF ADJUSTMENT VALUE 9. TEMPERATURE COMPENSATION OFFSET ADJUSTMENT10. LASER POWER ADJUSTMENT Setting Procedure11. TRAVERSE ADJUSTMENT – 27 –Specification Adjusting Procedure12.FOCUS BIAS ADJUSTMENT – 28 –Adjusting Procedure 13.ERROR RATE CHECK 15.AUTO GAIN CONTROL OUTPUT LEVEL ADJUSTMENT13-1.CD Error Rate Check 13-2.MO Error Rate CheckAdjustment Location – 30 –– BD BOARDSide A – – BD BOARDSide B –MDS-JE530 SECTION DIAGRAMS 6-1.BLOCK DIAGRAM – MD SERVO Section –– 31 – – 32 –6-2.BLOCK DIAGRAM – MAIN Section – MDS-JE530– 33 – – 34 –– 35 – Note on Printed Wiring BoardNote on Schematic Diagram – 36 – • Circuit Boards Location6-4.PRINTED WIRING BOARD – BD Board – – 38 –•See page 36 for Circuit Boards Location •Semiconductor Location– 39 – – 40 –MDS-JE530 6-6.SCHEMATIC DIAGRAM – BD Board 2/2 – See• – 41 –– 42 – MDS-JE5306-7.SCHEMATIC DIAGRAM – SW Board – 6-8.PRINTED WIRING BOARD – SW Board –– 43 – – 44 –6-9.PRINTED WIRING BOARD – MAIN Board – See• – 45 –– 46 – page 36 for Circuit Boards Location– 47 – – 48 –MDS-JE530 Page Page 41 Page– 49 – – 50 –MDS-JE530 – 51 – – 52 –MDS-JE530 • Semiconductor Location– 53 – – 54 –MDS-JE530 Page 47 Page•IC Block Diagrams – BD Board – – 55 –– 56 – IC101– 57 – IC310M5293L IC431– 58 – 6-14.IC PIN FUNCTION DESCRIPTION– 59 – •BD BOARD IC121 CXD2656R– 60 – – 61 – – 62 – •MAIN BOARD IC501 M30624MG-207FPSYSTEM CONTROLLER– 63 – – 64 – SECTION EXPLODED VIEWS – 65 –1CHASSIS SECTION 2FRONT PANEL SECTION 61 64 61 63 61 66 61 6151 53 59 54 52– 67 – 3MECHANISM SECTION MDM-5D 213 207202 201 223 207– 68 – 4BASE UNIT SECTION MBU-5D 252263 270 254 253SECTION ELECTRICAL PARTS LIST – 69 –DISPLAY – 70 –KEY SW – 71 –DISPLAY MAIN – 72 –KEY SW – 73 – MAIN– 74 – MAINPOWER SW – 75 –MAIN MDS-JE530 – 76 –Sony Corporation 9-928-824-11
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