Chapter 4
Detailed Example Design
This chapter provides detailed information about the example design, including a description of files and the directory structure generated by the Xilinx CORE Generator™ software, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the operation of the demonstration test bench.
<project directory>
<project_directory>/<component name>
Core release notes file
<component_name>/doc
Product documentation
<component_name>example design
Verilog and VHDL design files
<component_name>/implement
Implementation script files
<component_name>/implement/results
Results directory, created after implementation scripts are run, and contains implement script results
<component_name>/simulation
Simulation scripts
<component_name>/simulation/functional
Functional simulation files
simulation/timing
Simulation files
CAN Getting Started Guide | www.xilinx.com | 17 |
UG186 April 19, 2010