Xilinx 3.2 manual Functional Simulation, Timing Simulation

Page 16

Chapter 3: Quick Start Example Design

Functional Simulation

This section provides instructions for running a functional simulation of the CAN core using either VHDL or Verilog. Functional simulation models are provided when the core is generated. Implementing the core before simulating the functional models is not required.

To run a VHDL or Verilog functional simulation of the example design:

1.Set the current directory to:

<quickstart>/simulation/functional/

2.Launch the simulation script.

ModelSim: vsim -do simulate_mti.do

ncsim (ms-dos>):simulate_ncsim.bat

ncsim (Linux-shell%): ./simulate_ncsim.sh

The simulation script compiles the functional simulation models and demonstration test bench, adds relevant signals to the wave window, and runs the simulation. To observe the operation of the core, inspect the simulation transcript and the waveform.

Timing Simulation

Timing simulation is supported only for the Full-System Hardware Evaluation and Full license types, as the core cannot be implemented using a Simulation Only Evaluation license. This section contains instructions for running a timing simulation of the CAN core using either VHDL or Verilog. A timing simulation model is generated when the core is run through the Xilinx tools using the implement script. It is a requirement that the core is implemented before attempting to run timing simulation.

To run a VHDL or Verilog functional simulation of the example design:

1.Set the current directory to:

<quickstart>/simulation/timing/

2.Launch the simulation script:

ModelSim: vsim -do simulate_mti.do

ncsim (ms-dos>):simulate_ncsim.bat

ncsim (Linux-shell%): ./simulate_ncsim.sh

The simulation script compiles the timing simulation model and the demonstration test bench, adds relevant signals to the wave window, and runs the simulation. To observe the operation of the core, inspect the simulation transcript and the waveform.

16	www.xilinx.com	CAN Getting Started Guide
		UG186 April 19, 2010

Image 16

Contents LogiCORE IP can UG186 April 19Revision History Version RevisionTable of Contents Detailed Example Design Schedule of Figures 1Example DesignCan Getting Started Guide About This Guide Guide ContentsConventions Online Document Preface About This Guide Convention Meaning or Use ExampleIntroduction About the Core System RequirementsWindows LinuxRecommended Design Experience Additional Core ResourcesTechnical Support FeedbackLicensing the Core Before you BeginLicense Options Simulation OnlyInstalling Your License File Obtaining Your License KeyQuick Start Example Design OverviewGenerating the Core Quick Start Example DesignSetting up for Simulation Implementing the Example DesignSimulating the Example Design Implementing the Example DesignFunctional Simulation Timing SimulationDetailed Example Design Directory and File Contents Directory and File Contents Componentnameexample designComponentname/doc Name DescriptionComponentname/implement Componentname/implement/resultsComponentname/simulation 5Implement Directory Name DescriptionComponentname/simulation/functional Simulation/timing Simulation Scripts Implementation ScriptsImplementation Scripts Example Design Configuration 1illustrates the example design configurationTest Bench Functionality Demonstration Test BenchDemonstration Test Bench Core with Acceptance Filtering Customizing the Demonstration Test Bench Changing the DataDetailed Example Design