Xilinx 3.2 manual Simulation/timing

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Chapter 4: Detailed Example Design

simulation/timing

The timing simulation directory is generated only for Full-System Hardware Evaluation and Full-license types.

Table 4-9:Timing Directory

Name	Description

<project_dir>/<component_name>/simulation/timing

simulate_mti.do	A macro file for ModelSim that compiles the
	post-par timing netlist, demonstration test
	bench files, and runs the simulation.

simulate_ncsim.sh	A macro file for Cadence IES that compiles
	the post-par timing netlist, demonstration
	test bench files, and runs the simulation in a
	Linux environment.

simulate_ncsim.bat	A macro file for Cadence IES that compiles
	the post-par timing netlist, demonstration
	test bench files, and runs the simulation in a
	Windows environment.

wave.do	A macro file for ModelSim that opens a wave
	window and adds key signals to the wave
	viewer. This file is called by the
	simulate_mti.do file and is displayed after
	the simulation is loaded.

wave.sv	A macro file for Cadence IES that opens a
	wave window and adds key signals to the
	wave viewer.

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22	www.xilinx.com	CAN Getting Started Guide
		UG186 April 19, 2010

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Contents LogiCORE IP can UG186 April 19Revision History Version RevisionTable of Contents Detailed Example Design Schedule of Figures 1Example DesignCan Getting Started Guide About This Guide Guide ContentsConventions Online Document Preface About This Guide Convention Meaning or Use ExampleWindows IntroductionAbout the Core System Requirements LinuxTechnical Support Recommended Design ExperienceAdditional Core Resources FeedbackLicense Options Licensing the CoreBefore you Begin Simulation OnlyInstalling Your License File Obtaining Your License KeyQuick Start Example Design OverviewGenerating the Core Quick Start Example DesignSimulating the Example Design Setting up for SimulationImplementing the Example Design Implementing the Example DesignFunctional Simulation Timing SimulationDetailed Example Design Directory and File Contents Componentname/doc Directory and File ContentsComponentnameexample design Name DescriptionComponentname/simulation Componentname/implementComponentname/implement/results 5Implement Directory Name DescriptionComponentname/simulation/functional Simulation/timing Simulation Scripts Implementation ScriptsImplementation Scripts Example Design Configuration 1illustrates the example design configurationTest Bench Functionality Demonstration Test BenchDemonstration Test Bench Core with Acceptance Filtering Customizing the Demonstration Test Bench Changing the DataDetailed Example Design