Xilinx 3.2 manual Example Design Configuration, 1illustrates the example design configuration

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Chapter 4: Detailed Example Design

Timing Simulation

Note: Present only with a Full license.

The test scripts are a ModelSim or a Cadence IES macro that automates the simulation of the test bench. They are located in:

<project_dir>/<component_name>/simulation/timing/

The test script performs the following tasks:

•Compiles the SimPrim based gate level netlist simulation model

•Compiles the demonstration test bench

•Starts a simulation of the test bench

•Opens a Wave window and adds signals of interest (wave_mti.do/wave_ncsim.sv)

•Runs the simulation to completion

Example Design Configuration

Figure 4-1illustrates the example design configuration.

		CAN Example Design
	User		CAN Phy
	Interface	CAN Core	CAN Phy
	Interface	CAN Core	IOBs
	IOBs		IOBs
	IOBs
	Figure 4-1:Example Design Configuration

The example design contains the following:

•An instance of the CAN core

During simulation, the CAN core is instantiated as a black box and replaced with the CORE Generator software netlist during implementation and the gate-level simulation model.

•Input and output buffers for top-level port signal

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CAN Getting Started Guide

UG186 April 19, 2010

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Contents LogiCORE IP can UG186 April 19Revision History Version RevisionTable of Contents Detailed Example Design Schedule of Figures 1Example DesignCan Getting Started Guide Guide Contents About This GuideConventions Online Document Preface About This Guide Convention Meaning or Use ExampleIntroduction About the Core System RequirementsWindows LinuxRecommended Design Experience Additional Core ResourcesTechnical Support FeedbackLicensing the Core Before you BeginLicense Options Simulation OnlyInstalling Your License File Obtaining Your License KeyQuick Start Example Design OverviewGenerating the Core Quick Start Example DesignSetting up for Simulation Implementing the Example DesignSimulating the Example Design Implementing the Example DesignFunctional Simulation Timing SimulationDetailed Example Design Directory and File Contents Directory and File Contents Componentnameexample designComponentname/doc Name DescriptionComponentname/implement Componentname/implement/resultsComponentname/simulation 5Implement Directory Name DescriptionComponentname/simulation/functional Simulation/timing Implementation Scripts Simulation ScriptsImplementation Scripts Example Design Configuration 1illustrates the example design configurationDemonstration Test Bench Test Bench FunctionalityDemonstration Test Bench Core with Acceptance Filtering Customizing the Demonstration Test Bench Changing the DataDetailed Example Design