Xilinx 3.2 manual Demonstration Test Bench, Test Bench Functionality

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Demonstration Test Bench

Demonstration Test Bench

Figure 4-2illustrates the demonstration test bench.

Clock

Generator

Stimulus

Generator

Checker

Demonstration Test Bench

 

CAN Example Design

 

User

CAN Core

CAN Phy

Interface

IOBs

IOBs

 

 

 

Figure 4-2:Demonstration Test Bench

 

Test Bench Functionality

The demonstration test bench is a straightforward VHDL or Verilog file to exercise the example design and the core itself.

The test bench consists of the following:

•Clock Generators

•Procedure to write to a Configuration Register memory location

•Procedure to read from a Configuration Register memory location

•Procedure to display the bits set in the Interrupt Status Register (ISR)

Core with No Acceptance Filtering

The demonstration test bench performs the following tasks:

•Input clock signals are generated.

•A reset is applied to the example design.

•The Baud Rate Prescalar register and Bit Timing registers are written to. These registers are read from and the values read are compared with the values written.

•The Interrupt Enable Register is written to enable interrupts for TXBFLL and RXOK bits. This register is read from and the value read is compared with the value written.

•The Mode Select Register is written to select Loop Back mode of operation. This register is read from and the value read is compared with the value written.

•The Software Reset Register is written to enable CEN bit. This register is read from and the value written is compared with the value read.

CAN Getting Started Guide

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UG186 April 19, 2010

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Contents UG186 April 19 LogiCORE IP canVersion Revision Revision HistoryTable of Contents Detailed Example Design 1Example Design Schedule of FiguresCan Getting Started Guide About This Guide Guide ContentsConventions Preface About This Guide Convention Meaning or Use Example Online DocumentAbout the Core System Requirements IntroductionWindows LinuxAdditional Core Resources Recommended Design ExperienceTechnical Support FeedbackBefore you Begin Licensing the CoreLicense Options Simulation OnlyObtaining Your License Key Installing Your License FileOverview Quick Start Example DesignQuick Start Example Design Generating the CoreImplementing the Example Design Setting up for SimulationSimulating the Example Design Implementing the Example DesignTiming Simulation Functional SimulationDetailed Example Design Directory and File Contents Componentnameexample design Directory and File ContentsComponentname/doc Name DescriptionComponentname/implement/results Componentname/implementComponentname/simulation 5Implement Directory Name DescriptionComponentname/simulation/functional Simulation/timing Simulation Scripts Implementation ScriptsImplementation Scripts 1illustrates the example design configuration Example Design ConfigurationTest Bench Functionality Demonstration Test BenchDemonstration Test Bench Core with Acceptance Filtering Changing the Data Customizing the Demonstration Test BenchDetailed Example Design
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