Xilinx 3.2 manual Introduction, About the Core System Requirements, Windows, Linux, Software

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Chapter 1

Introduction

The LogiCORE™ IP CAN v3.2 core is a compact, full-featured targeted design platform that conforms to ISO 11898-1, CAN2.0A and CAN2.0B standards. Bit rates of up to 1 Mbps are supported. The core size can be optimized using parameterized configurations for acceptance filtering and FIFO depth. The example design in this guide is provided in both Verilog and VHDL.

This chapter introduces the CAN core and provides related information, including system requirements, recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

About the Core

The CAN core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see www.xilinx.com/xlnx/xebiz/designResources/ip_product_details. For information about licensing options, see Chapter 2, “Licensing the Core.”

System Requirements

Windows

•Windows XP 2000 Professional 32-bit/64-bit

•Windows Vista Business 32-bit/64-bit

Linux

•Red Hat Enterprise Linux WS v4.0 32-bit/64-bit

•Red Hat Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option)

•SUSE Linux Enterprise (SLE) desktop and server v10.1 32-bit/64-bit

Software

•ISE® software v12.1

•Mentor Graphics ModelSim v6.5c and above

•Cadence Incisive Enterprise Simulator (IES) v9.2 and above

•Synopsys VCS and VCS MX 2009.12 and above

CAN Getting Started Guide

www.xilinx.com

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UG186 April 19, 2010

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Contents UG186 April 19 LogiCORE IP canVersion Revision Revision HistoryTable of Contents Detailed Example Design 1Example Design Schedule of FiguresCan Getting Started Guide Guide Contents About This GuideConventions Preface About This Guide Convention Meaning or Use Example Online DocumentAbout the Core System Requirements IntroductionWindows LinuxAdditional Core Resources Recommended Design ExperienceTechnical Support FeedbackBefore you Begin Licensing the CoreLicense Options Simulation OnlyObtaining Your License Key Installing Your License FileOverview Quick Start Example DesignQuick Start Example Design Generating the CoreImplementing the Example Design Setting up for SimulationSimulating the Example Design Implementing the Example DesignTiming Simulation Functional SimulationDetailed Example Design Directory and File Contents Componentnameexample design Directory and File ContentsComponentname/doc Name DescriptionComponentname/implement/results Componentname/implementComponentname/simulation 5Implement Directory Name DescriptionComponentname/simulation/functional Simulation/timing Implementation Scripts Simulation ScriptsImplementation Scripts 1illustrates the example design configuration Example Design ConfigurationDemonstration Test Bench Test Bench FunctionalityDemonstration Test Bench Core with Acceptance Filtering Changing the Data Customizing the Demonstration Test BenchDetailed Example Design
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