Texas Instruments DAC8555EVM manual Optional Signal Conditioning Op-Amp U4B, Jumper Settings

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EVM Operation

3.4.3Capacitive Load Drive

It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op amps may become unstable, depending on the op amp configuration, gain, and load value. These factors are just few of the issues that can affect op amp stability and should be considered during implementation.

In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads. Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistor even improves the capacitive load drive capability.

Table 6 shows the jumper setting configuration for a capacitive load drive.

Table 6. Capacitive Load Drive Output Jumper Settings

Jumper Setting

Reference Unipolar Bipolar

JMP5 Open Open

JMP10 2-3 1-2

JMP6 Open Open

Function

VREFH is disconnected from the inverting input of the output op amp U2.

Supplies power, VSS, to the negative rail of op amp U2 for bipolar mode, or ties it to AGND for unipolar mode.

Capacitive load drive output of DAC is routed to pin 2 of JMP6 and may be used as the output terminal.

3.5Optional Signal Conditioning Op-Amp (U4B)

One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the other half is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desires to implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not

populated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so it is up to the user on how to connect the (±) input signals to this op amp. No test point has been made available for the output because of space restrictions, but a wire can be soldered to the output of the op amp via an unused component pad that connects to it. The op amp circuit can be configured by populating the corresponding components to those that match the circuit design while leaving all other unused component footprints unpopulated.

3.6Jumper Settings

Table 7 shows the function of each specific jumper setting of the EVM.

 

Table 7. Jumper Settings and Functions

Reference

Jumper Setting (1) Function

 

ENABLE pin is set high through pull-up resistor R1. ENABLE can be driven by GPIO2,

 

J2-8.

JMP1

 

 

ENABLE pin is set low and DAC is enabled.

 

LDAC pin is set high through pull-up resistor R2. LDAC can be driven by GPIO0, J2-2.

JMP2

 

 

LDAC pin is set low and DAC update is accomplished via software.

 

RSTSEL pin is set high through pull-up resistor R3. RSTSEL can be driven by GPIO4,

 

J2-14.

JMP3

 

 

RSTSEL pin is set low.

(1)Indicates the corresponding pins that are shorted or closed.

SLAU204 –December 2006

DAC8555EVM User's Guide

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Contents DAC8555EVM Users Guide Overview PCB Design and Performance EVM Operation Schematic Reference Voltage FeaturesPower Requirements Supply VoltageEVM Basic Functions DAC8555EVM Functional Block Diagram PCB Layout PCB Design and PerformanceDAC8555EVM PCB-Top Silkscreen Image DAC8555EVM PCB-Layer 2 Ground Plane DAC8555EVM PCB-Layer 4 Bottom Signal Layer DAC8555EVM-Drill Drawing EVM PerformanceINL and DNL Characterization Graph of DAC a INL and DNL Characterization Graph of DAC B INL and DNL Characterization Graph of DAC C INL and DNL Characterization Graph of DAC D Bill of Materials DAC8555EVM Parts ListEVM Stacking Default SettingsFactory Default Jumper Settings Host Processor InterfaceDAC Output Channel Mapping Output Op AmpOutput Gain Unity Gain Output Jumper SettingsOutput Gain of 2 Jumper Settings Unity Gain OutputJumper Settings and Functions Optional Signal Conditioning Op-Amp U4BJumper Settings Capacitive Load Drive Output Jumper SettingsReference JMP12 JMP13 JMP14 JMP15 JMP16 Schematic Ti a Evaluation BOARD/KIT Important Notice FCC WarningImportant Notice