Texas Instruments DAC8555EVM Features, Power Requirements, Supply Voltage, Reference Voltage

Page 3

www.ti.com

Overview

1Overview

This section gives a general overview of the DAC8555EVM and describes some of the factors that must be considered when using this demonstration board.

1.1Features

The DAC8555EVM is a simple evaluation module designed for a quick and easy way to evaluate the functionality and performance of the high-resolution, quad-channel, serial input DAC8555 digital-to-analog converter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TI DSP-based system.

1.2Power Requirements

This subsection describes the power requirements for this device.

1.2.1Supply Voltage

The DC power supply requirement for the digital section (VDD) of this EVM is typically +5V connected to the J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card) and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements for the analog section of this EVM are: VCC and VSS range from +15.75V to –15.75V (maximum), connecting through J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5VA connects through terminals J5-3 or J3-3, and the +3.3VA connects through terminal J3-8. All of the analog power supplies are referenced to analog ground through terminals J1-2 and J3-6.

The analog power supply for the device under test, U1, can be powered by either +5VA or +3.3VA by selecting the proper position of jumper JMP7. This configuration allows the DAC8555 analog section to operate from either supply power while the I/O and digital section are powered by +5V, VDD.

The VCC supply source is primarily used to provide the positive rail of the external output op amp, U2, the reference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can be selected between VSS and AGND via jumper JMP10. The external op amp is installed as an option to provide output signal conditioning or to boost capacitive load drive, or for other desired output mode requirements.

CAUTION

To avoid potential damage to the EVM board, be sure that the correct cables are connected to their respective terminals as labeled on the EVM board. Stresses above the maximum listed voltage ratings may cause permanent damage to the device.

1.2.2Reference Voltage

The +5V precision voltage reference is provided to supply the external voltage reference for the DAC through the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes through an adjustable 100kΩ potentiometer, R15, in series with 20kΩ, R16, to allow the user to adjust the reference voltage to its desired settings. The voltage reference is then buffered through U4A as seen by the device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, in order to allow the user to connect another external reference source if the onboard reference circuit is not desired. The external voltage reference should not exceed +5V DC.

The REF02 precision reference is powered by VCC (+15V) through either terminal J1-3 or J3-1.

SLAU204 –December 2006

DAC8555EVM User's Guide

3

Submit Documentation Feedback

Image 3
Contents DAC8555EVM Users Guide Overview PCB Design and Performance EVM Operation Schematic Reference Voltage FeaturesPower Requirements Supply VoltageEVM Basic Functions DAC8555EVM Functional Block Diagram PCB Layout PCB Design and PerformanceDAC8555EVM PCB-Top Silkscreen Image DAC8555EVM PCB-Layer 2 Ground Plane DAC8555EVM PCB-Layer 4 Bottom Signal Layer DAC8555EVM-Drill Drawing EVM PerformanceINL and DNL Characterization Graph of DAC a INL and DNL Characterization Graph of DAC B INL and DNL Characterization Graph of DAC C INL and DNL Characterization Graph of DAC D Bill of Materials DAC8555EVM Parts ListEVM Stacking Default SettingsFactory Default Jumper Settings Host Processor InterfaceDAC Output Channel Mapping Output Op AmpOutput Gain Unity Gain Output Jumper SettingsOutput Gain of 2 Jumper Settings Unity Gain OutputJumper Settings and Functions Optional Signal Conditioning Op-Amp U4BJumper Settings Capacitive Load Drive Output Jumper SettingsReference JMP12 JMP13 JMP14 JMP15 JMP16 Schematic Ti a Evaluation BOARD/KIT Important Notice FCC WarningImportant Notice