Texas Instruments DAC8555EVM manual Reference

Page 20

www.ti.com

EVM Operation

Table 7. Jumper Settings and Functions (continued)

Reference

Jumper Setting (1)

JMP4

JMP5

JMP6

1 3

JMP7

1 3

1 3

JMP8

1 3

1 3

JMP9

1 3

1 3

JMP10

1 3

1 3

JMP11

1 3

Function

RST pin is set high through pull-up resistor R4. RST can be driven by GPIO5, J2-19.

RST pin is set low.

Disconnects VREFH to the inverting input of the op amp U2.

Connects VREFH to the inverting input of the op amp U2.

Disconnects the inverting input of the op amp U2 from the gain resistor, R9.

Connects the inverting input of the op amp U2 from the gain resistor, R9 for output gain of 2.

+5V analog supply is selected for AVDD.

+3.3V analog supply is selected for AVDD.

Routes the adjustable, buffered, onboard +5V reference to the VREFH input of the DAC8555.

Routes the user-supplied reference from TP2 or J4-20 to the VREFH input of the DAC8555.

VREFL is tied to AGND.

Routes the user-supplied negative reference from TP3 or J4-18 to the VREFL input of the DAC8555. This voltage should be within the range of 0V to VREFH.

Negative supply rail of the op amp U2 is powered by VSS for bipolar operation.

Negative supply rail of the op amp U2 is tied to AGND for unipolar operation.

Routes VOUTA to J4-2.

Routes VOUTA to J4-10.

20

DAC8555EVM User's Guide

SLAU204 –December 2006

 

 

Submit Documentation Feedback

Image 20
Contents DAC8555EVM Users Guide Overview PCB Design and Performance EVM Operation Schematic Features Power RequirementsSupply Voltage Reference VoltageEVM Basic Functions DAC8555EVM Functional Block Diagram PCB Design and Performance PCB LayoutDAC8555EVM PCB-Top Silkscreen Image DAC8555EVM PCB-Layer 2 Ground Plane DAC8555EVM PCB-Layer 4 Bottom Signal Layer EVM Performance DAC8555EVM-Drill DrawingINL and DNL Characterization Graph of DAC a INL and DNL Characterization Graph of DAC B INL and DNL Characterization Graph of DAC C INL and DNL Characterization Graph of DAC D DAC8555EVM Parts List Bill of MaterialsDefault Settings Factory Default Jumper SettingsHost Processor Interface EVM StackingOutput Op Amp DAC Output Channel MappingUnity Gain Output Jumper Settings Output Gain of 2 Jumper SettingsUnity Gain Output Output GainOptional Signal Conditioning Op-Amp U4B Jumper SettingsCapacitive Load Drive Output Jumper Settings Jumper Settings and FunctionsReference JMP12 JMP13 JMP14 JMP15 JMP16 Schematic Ti a FCC Warning Evaluation BOARD/KIT Important NoticeImportant Notice