Telex C-2002 technical manual System Clock Generation, Non-Volatile Memory Eeprom, User I/O

12 Vega’s C-2002

6.4 System Clock Generation

The system clock is derived from a single 32.7680MHz Crystal Oscillator (Y1). The ADSP2189 DSP (U1) processor uses this clock to generate a 65.536MHz internal instruction clock rate. The system clock is routed to the Altera EPM7032AE44 PLD (U5) and divided into the signals necessary for audio processing. These signals include the MCLK (2.048MHz), SCLK (512kHz), LRCLK (8kHz) and FS (16kHz frame sync). Another signal generate by the PLD is B0 (U5-28). This signal is used by DSP software to sync the bit frames at start up. B0 is the inverse of LRCLK. U5-31 is a clock signal that is the inverse of SCLK. The DSP serial port requires this signal, usually called the bit clock.

6.5 Non-Volatile Memory (EEPROM)

All the system configuration and parameter storage is maintained in the non-volatile memory of U3. The serial EEPROM AT24C16, has 16kbits of memory. The DSP writes and reads to the EEPROM via two of its Flag Pins.

6.6 User I/O

The Keypad and Seven Segment display are the main components to the User I/O scheme. The DSP controls the I/O with a series of register and latches (U22, U23, U26, U27, U28, U16). Chip Selects originate from the DSP, but are modified to their usable state by the PLD. The Chip selects are R-CS0,1(read) and W-CS0,1,2,3(write). They are generated by DSP signals RD, WR, IOMS and address lines A0,A1,A5.

6.7 Clone Mode Serial Port

The C-2002 can be used to copy the memory contents of one C-2002 to another. This is done with the serial data port on the back of the unit (J3). The circuitry used is a simple level conversion scheme to take the 3.3Vdc serial data stream from the DSP and convert it to a 10Vdc signal at the port. The port can only be used C-2002-to-C-2002. A standard 16C550 UART U18 is included in the DSP’s memory map. The UART levels are converted to standard RS-232C by U20. The C-2002 firmware code can be updated through this port from any Windows 9x or greater PC. See the www.vega-signaling.com website for software updates.

6.8 Power Regulation and Reset Control

Input power is a 12Vdc wall mount regulator. The input connector (J35) is a center positive, 2.5mm jack. It is connected to protection circuitry consisting of a fuse and dual diodes used to protect the source if auxiliary power is connected to J36. The system DC power requirements are 3.3V and 2.5V(U8) for the DSP and 5V(U6), 10V(U7) for the analog circuitry.