Texas Instruments TMS320C6201 manuals

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TMS320C6201 Silicon Errata
2Contents
- 3TMS320C6201 Silicon Errata
- 41 Introduction
  - 1.1 Quality and Reliability Conditions
5DSP
- SPRZ153
- 6TMS320C6201 Silicon Errata
  - 6
- 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051)
  - Table 2. Timing Requirements for Interrupt Response Cycles
  - Table 3. JTAG Test-Port Timing
  - Figure 2. SBSRAM Read Timing (1/2 Rate SSCLK) (See Note)
  - 7Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note)
- 83 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications
  - Issues When Pausing at a Block Boundary
  - DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame
  - Advisory 3.1.1
- - Advisory 3.1.2
  - DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional
  - Advisory 3.1.3
  - DMA Freezes if Postincrement/Decrement Across Port Boundary
  - DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync
  - Advisory 3.1.4
  - Advisory 3.1.5
- 9
  - DMA Paused During Emulation Halt
  - Advisory 3.1.6
  - EMIF: Invalid SDRAM Access to Last 1K Byte of CE3
  - DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync
  - Advisory 3.1.7
  - Advisory 3.1.8
- 10
  - Cache During Emulation With Extremely Slow External Memory
  - Advisory 3.1.9
- 11
- 124 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications
  - EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz
  - Advisory 3.0.8
  - Figure 4. Write Example Desired Behavior
  - Figure 5. Write Example Failing Behavior
  - EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued)
  - Figure 6. Read Example Desired Behavior
  - Figure 7. Read Example Failing Behavior
- 13
  - 16EMIF: SDRAM Invalid Access (Continued)
  - DMA: RSYNC Cleared Late for Frame-synchronized Transfer
  - McBSP: DXR to XSR Copy Not Generated
  - Advisory 2.1.4
  - Advisory 2.1.5
  - 18McBSP: DXR to XSR Copy Not Generated (Continued)
  - DMA Split-mode End-of-frame Indexing
  - Advisory 2.1.6
- 20TMS320C6201 Silicon Errata
  - McBSP: Incorrect mLaw Companding Value
  - EMIF: HOLD Feature Improvement on Revision 3
  - False Cache Hit Extremely Rare
  - Advisory 2.1.11
  - Advisory 2.1.12
- - Advisory 2.1.13
  - 21EMIF: HOLD Request Causes Problems With SDRAM Refresh
  - Advisory 2.1.14
  - DMA Priority Ignored by PBUS
  - Advisory 2.1.15
- 246 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications
- 25
  - EMIF: Data Setup Times
  - Advisory 2.0.19
  - EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur
  - Advisory 2.0.24
- 287 Documentation Support