SPRZ153
TMS320C6201 Silicon Errata6
2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051)Table 2. Timing Requirements for Interrupt Response Cycles
NO
C6201B
UNIT
NO. MIN MAX UNIT
4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid –4 6 ns
5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 6 ns
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid –4 ns
Table 3. JTAG Test-Port Timing
NO.
C6201,
C6201B UNIT
NO.
MIN MAX
UNIT
1 Tc(TCK) Cycle time, TCK 50 ns
4 Th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
Figure 2. SBSRAM Read Timing (1/2 Rate SSCLK) (See Note)
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
65
43
21
8
7
SSCLK
BE_ [3:0]
EA [21:2]
ED [31:0]
CE
SSADS
SSOE
SSWE