TMS320C6201 Silicon Errata | SPRZ153 |
Advisory 2.1.14
Revision(s) Affected:
Details:
Workaround:
EMIF: HOLD Request Causes Problems With SDRAM Refresh
2.1 and 2.0
If the HOLD interface is used in a system with SDRAM, there are some situations that are likely to occur.
If the NOHOLD bit is not set and an external requester attempts to gain control of the bus via the HOLD signal of the EMIF at the exact same time when the EMIF is issuing a SDRAM Refresh command, the HOLD request is never recognized. Even if the NOHOLD bit is set in the EMIF Global Control Register, SDRAM refreshes are still disabled as long as the HOLD request is pending. A single refresh after receiving the HOLD request is issued, but no additional refreshes are issued until the HOLD request is removed. The C62xt still owns the bus since the NOHOLD bit is set.
In addition, if an SDRAM burst is started just prior to a HOLD request, it is possible that the request will not be recognized until a refresh occurs. This will potentially allow for the HOLD request to be ignored for several microseconds. (Internal reference number 0757 and 0777)
Do not allow a requester to activate the HOLD line without acknowledging it for longer than the SDRAM refresh period. A workaround can be accomplished by keeping the NOHOLD bit set and
Upon detecting a HOLD request, SDRAM refreshes are disabled, NOHOLD bit is cleared, and a pulse is generated on the input HOLD signal (can use DMACx as a
Advisory 2.1.15
Revision(s) Affected:
Details:
Workaround:
DMA Priority Ignored by PBUS
2.1 and 2.0
The CPU always has priority over the DMA when accessing peripherals. The DMA PRI bit is ignored and treated as “0”. (Internal reference number 0540)
Leave sufficient gaps in CPU accesses to the PBUS to allow the DMA time to gain adequate access.
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