TMS320C6201 Silicon Errata | SPRZ153 |
Advisory 3.1.6
Revision(s) Affected:
Details:
Workaround:
Advisory 3.1.7
Revision(s) Affected:
Details:
Workaround:
Advisory 3.1.8
Revision(s) Affected:
Details:
Workaround:
DMA Paused During Emulation Halt
3.1, 3.0, 2.1, and 2.0
When running an autoinitialized transfer, the DMA write state machine is halted during an emulation halt regardless of the value of EMOD in the DMA Channel Primary Control Register. The read state machine functions properly in this case. The problem exists only at block boundaries. If EMOD = 1, this problem is irrelevant since the DMA channel is expected to pause during an emulation halt. (Internal reference number C601301)
There is no workaround for EMOD = 0. Expect DMA transfers to pause when the emulator stops the processor.
DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync
3.1, 3.0, 2.1, and 2.0
If RSYNC in the DMA Channel Primary Control Register is set to
Do not use synchronized DMA reads to DSPINT. If a DMA read is desired during a
EMIF: Invalid SDRAM Access to Last 1K Byte of CE3
3.1, 3.0, 2.1, and 2.0
If 16M bytes of SDRAM (two 64M bits in a 1M X 16x4 organization) is used in CE3, you can have invalid accesses to the last 1K byte of CE3 (0x03FFFC00).
This occurs when the following is true:
•After a DCAB (deactivate all pages) to all SDRAM CE spaces (forced by Refresh or MRS command)
•The first access to CE3 is to the last page of CE3 (0x03FFFC00).
•Then a page activate will not be issued to CE3. Since the SDRAM in CE3 is in a deactivated state at that point, invalid accesses will occur. (Internal reference number C630280)
Best Case: Avoid designing a board with a
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