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Texas Instruments TMS320C6201 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications

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SPRZ153

TMS320C6201 Silicon Errata

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4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications

EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz

Advisory 3.0.8

Revision(s) Affected: 3.0, 2.1, and 2.0

Details: A speedpath in the device causes SDCLK and SSCLK to start up 180 degrees out-of-phase

(effectively inverted) from the desired waveform. Normally, EMIF outputs are delayed 1/2 CPU

clock from the rising edge of SDCLK/SSCLK to give it adequate hold time while maintaining

more than adequate setup times.

The desired relationship is described in the TMS320C6201B data sheet (SPRS051) and is

illustrated in Figure 4 and Figure 6. However, in the case where SDCLK/SSCLK becomes

inverted (Figure 5 and Figure 7), control signals only have 1/2 CPU clock of setup to the next

SDCLK/SSCLK rising rather than 3/2 CPU clock of setup. This has two negative effects to

interface timing to external synchronous RAMs.

1. On writes, setup time to RAMs for control signals and write data is reduced by 1 CPU cycle.

Figure 4. Write Example – Desired Behavior

tohtosu

CLKOUT1 (CPU Clock)

SS/SDCLK Internal

SS/SDCLK External

Output Signals

Figure 5. Write Example – Failing Behavior

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tosu

CLKOUT1 (CPU Clock)

SS/SDCLK Internal

SS/SDCLK External

Output Signals

Contents

Main TMS320C6201 Silicon Errata Contents TMS320C6201 Silicon Errata 1 Introduction 1.1 Quality and Reliability Conditions DSP SPRZ153 TMS320C6201 Silicon Errata 6 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) Table 2. Timing Requirements for Interrupt Response Cycles Table 3. JTAG Test-Port Timing Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note) 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Issues When Pausing at a Block Boundary DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame Advisory 3.1.1 Advisory 3.1.2 Cache During Emulation With Extremely Slow External Memory Advisory 3.1.9 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Advisory 3.0.8 Figure 4. Write Example Desired Behavior Figure 5. Write Example Failing Behavior Page Page EMIF: SDRAM Invalid Access (Continued) DMA: RSYNC Cleared Late for Frame-synchronized Transfer McBSP: DXR to XSR Copy Not Generated Advisory 2.1.4 Advisory 2.1.5 Page McBSP: DXR to XSR Copy Not Generated (Continued) DMA Split-mode End-of-frame Indexing Advisory 2.1.6 Page TMS320C6201 Silicon Errata McBSP: Incorrect mLaw Companding Value EMIF: HOLD Feature Improvement on Revision 3 False Cache Hit Extremely Rare Advisory 2.1.11 EMIF: HOLD Request Causes Problems With SDRAM Refresh Advisory 2.1.14 DMA Priority Ignored by PBUS Advisory 2.1.15 Page Page 6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications Page Page Page EMIF: Data Setup Times Advisory 2.0.19 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur Advisory 2.0.24 7 Documentation Support