Texas Instruments TMS320C6201 - page 11

SPRZ153

TMS320C6201 Silicon Errata

11

Alternative: If a 64M-bit SDRAM is located in CE3, avoid using the last 1K byte in the CE3

memory map (0x03FFFC00).

Cache During Emulation With Extremely Slow External Memory

Advisory 3.1.9

Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0

Details: If a program requests fetch packet “A” followed immediately by fetch packet “B”, and all of the

following four conditions are true:

1. A and B are separated by a multiple of 64K in memory (i.e., they will occupy the same

cache frame)

2. B is currently located in cache

3. You are using the emulator to single-step through the branch from A to B

4. The code is running off of an extremely slow external memory that transfers one 32-bit

word every 8000 or more CPU clock cycles (CPU running at 200 MHz)

Then A will be registered as a “miss” and B will be registered as a “hit”. B will not be reloaded

into cache, and A will be executed twice. This condition is extremely rare because B has to be

in cache memory, and must be the next fetch packet requested after A (which is not in cache

memory). In addition, this problem only occurs if you single-step through the branch from A to

B using the emulator, and if the code is located in an extremely slow external memory.

(Internal reference number C630283)

Workaround:•Do not single-step through the branch from A to B if the above conditions are true.

•Do not use an extremely slow external memory (transfers one 32-bit word every 8000

or more CPU clock cycles) if conditions 1, 2, and 3 are true.

Contents

Main TMS320C6201 Silicon Errata Contents TMS320C6201 Silicon Errata 1 Introduction 1.1 Quality and Reliability Conditions DSP SPRZ153 TMS320C6201 Silicon Errata 6 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) Table 2. Timing Requirements for Interrupt Response Cycles Table 3. JTAG Test-Port Timing Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note) 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Issues When Pausing at a Block Boundary DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame Advisory 3.1.1 Advisory 3.1.2 Cache During Emulation With Extremely Slow External Memory Advisory 3.1.9 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Advisory 3.0.8 Figure 4. Write Example Desired Behavior Figure 5. Write Example Failing Behavior Page Page EMIF: SDRAM Invalid Access (Continued) DMA: RSYNC Cleared Late for Frame-synchronized Transfer McBSP: DXR to XSR Copy Not Generated Advisory 2.1.4 Advisory 2.1.5 Page McBSP: DXR to XSR Copy Not Generated (Continued) DMA Split-mode End-of-frame Indexing Advisory 2.1.6 Page TMS320C6201 Silicon Errata McBSP: Incorrect mLaw Companding Value EMIF: HOLD Feature Improvement on Revision 3 False Cache Hit Extremely Rare Advisory 2.1.11 EMIF: HOLD Request Causes Problems With SDRAM Refresh Advisory 2.1.14 DMA Priority Ignored by PBUS Advisory 2.1.15 Page Page 6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications Page Page Page EMIF: Data Setup Times Advisory 2.0.19 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur Advisory 2.0.24 7 Documentation Support