Texas Instruments TMS320C6201 manual DMA Split-mode Receive Transfer Incomplete After Pause

TMS320C6201 Silicon Errata SPRZ153

Advisory 2.1.16

Revision(s) Affected:

Details:

Workaround:

Advisory 2.1.17

Revision(s) Affected:

Details:

Workaround:

Advisory 2.1.18

Revision(s) Affected:

Details:

DMA Split-mode Receive Transfer Incomplete After Pause

2.1 and 2.0

If the DMA is performing a split-mode transfer and the channel is paused after all Transmit Reads in a frame are completed but before the Receive Reads are completed, then the Receive Transfer will not complete after the channel is restarted. (Internal reference number 0606)

Do not pause a split-mode transfer at the end of a frame unless the frame has completed.

DMA Multiframe Transfer Data Lost During Stop

2.1 and 2.0

If the DMA is stopped while performing an unsynchronized, multiframe transfer, all of the read data may not be written. The data will be written when the channel is restarted. This case will only occur when the frame size (element count) is 10 or less and data elements from multiple frames are in the FIFO when it is stopped. (Internal reference number 0789)

Keep frame size > 10, synchronize the frame (FS = 1), or do not stop the transfer.

Bootload: HPI Feature Improvement on Revision 3

2.1 and 2.0

This is documented as a difference between the TMX320C6201 revision 2.x (and earlier) and revision 3.0 (and later).

Currently, during HPI boot, all accesses to program memory are treated as writes by the PMEMC. This means that the host may not read the internal program memory space, as doing so will overwrite the memory space, usually with all zeros. The PMEMC will be changed to differentiate between reads and writes to program memory during boot. (Internal reference number 0604)

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