Texas Instruments TMS320C6201 DSP

SPRZ153

TMS320C6201 Silicon Errata

1.2 Revision Identification

The device revision can be determined by the lot trace code marked on the top of the package. The

location for the lot trace codes for the GJL package is shown in Figure 1 and the revision numbers are

listed in Table 1.

Figure 1. Example, Lot Trace Code for TMS320C6201

DSP

TMS320C6201GJL

Cxx–YMLLLLS

DSP

TMS320C6201GJL

C31–YMLLLLS

Lot trace code with revision 3.1

Lot trace code

NOTE:Qualified devices are marked with the letters “TMS” at the beginning of the device name, while nonqualified devices are marked with

the letters “TMX” at the beginning of the device name.

Table 1. Lot Trace Number Names

Lot Trace Code Silicon Revision Comments

20 2.0

21 2.1

30 3.0

31 3.1

Contents

Main TMS320C6201 Silicon Errata Contents TMS320C6201 Silicon Errata 1 Introduction 1.1 Quality and Reliability Conditions DSP SPRZ153 TMS320C6201 Silicon Errata 6 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) Table 2. Timing Requirements for Interrupt Response Cycles Table 3. JTAG Test-Port Timing Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note) 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Issues When Pausing at a Block Boundary DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame Advisory 3.1.1 Advisory 3.1.2 Cache During Emulation With Extremely Slow External Memory Advisory 3.1.9 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Advisory 3.0.8 Figure 4. Write Example Desired Behavior Figure 5. Write Example Failing Behavior Page Page EMIF: SDRAM Invalid Access (Continued) DMA: RSYNC Cleared Late for Frame-synchronized Transfer McBSP: DXR to XSR Copy Not Generated Advisory 2.1.4 Advisory 2.1.5 Page McBSP: DXR to XSR Copy Not Generated (Continued) DMA Split-mode End-of-frame Indexing Advisory 2.1.6 Page TMS320C6201 Silicon Errata McBSP: Incorrect mLaw Companding Value EMIF: HOLD Feature Improvement on Revision 3 False Cache Hit Extremely Rare Advisory 2.1.11 EMIF: HOLD Request Causes Problems With SDRAM Refresh Advisory 2.1.14 DMA Priority Ignored by PBUS Advisory 2.1.15 Page Page 6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications Page Page Page EMIF: Data Setup Times Advisory 2.0.19 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur Advisory 2.0.24 7 Documentation Support