Texas Instruments TMS320C6201 1 Introduction

SPRZ153

TMS320C6201 Silicon Errata

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1 Introduction

This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon

releases 3.1, 3.0, 2.1, and 2.0.

1.1 Quality and Reliability Conditions

TMX Definition

Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability

for products classified as “TMX.” By definition, the product has not completed data sheet verification or reliability

performance qualification according to TI Quality Systems Specifications.

The mere fact that a “TMX” device was tested over a particular temperature and voltage ranges should not, in any

way, be construed as a warranty of performance.

TMP Definition

TI does not warranty product reliability for products classified as “TMP.” By definition, the product has not

completed reliability performance qualification according to TI Quality Systems Specifications; however, products

are tested to a published electrical and mechanical specification.

TMS Definition

Fully-qualified production device.

Contents

Main TMS320C6201 Silicon Errata Contents TMS320C6201 Silicon Errata 1 Introduction 1.1 Quality and Reliability Conditions DSP SPRZ153 TMS320C6201 Silicon Errata 6 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) Table 2. Timing Requirements for Interrupt Response Cycles Table 3. JTAG Test-Port Timing Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note) 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Issues When Pausing at a Block Boundary DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame Advisory 3.1.1 Advisory 3.1.2 Cache During Emulation With Extremely Slow External Memory Advisory 3.1.9 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Advisory 3.0.8 Figure 4. Write Example Desired Behavior Figure 5. Write Example Failing Behavior Page Page EMIF: SDRAM Invalid Access (Continued) DMA: RSYNC Cleared Late for Frame-synchronized Transfer McBSP: DXR to XSR Copy Not Generated Advisory 2.1.4 Advisory 2.1.5 Page McBSP: DXR to XSR Copy Not Generated (Continued) DMA Split-mode End-of-frame Indexing Advisory 2.1.6 Page TMS320C6201 Silicon Errata McBSP: Incorrect mLaw Companding Value EMIF: HOLD Feature Improvement on Revision 3 False Cache Hit Extremely Rare Advisory 2.1.11 EMIF: HOLD Request Causes Problems With SDRAM Refresh Advisory 2.1.14 DMA Priority Ignored by PBUS Advisory 2.1.15 Page Page 6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications Page Page Page EMIF: Data Setup Times Advisory 2.0.19 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur Advisory 2.0.24 7 Documentation Support