Texas Instruments TMS320C6201 instruction

TMS320C6201

Digital Signal Processor

Silicon Errata

SPRZ153

November 2000

Copyright  2000, Texas Instruments Incorporated

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Texas Instruments manual TMS320C6201 Digital Signal Processor Silicon Errata

Contents

TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block Boundary DMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Read Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid Access McBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized Transfer For big-endian mode DMA Split-mode End-of-frame Indexing Power-Down Pin PD Not Set High for Power-Down 2 Mode Timer Clock Output Not Driven for External ClockDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not Functional McBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram Refresh DMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to Internal Program Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of Block Emif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup Times Important Notice