Texas Instruments TMS320C6201 manual DMA Split-mode End-of-frame Indexing

TMS320C6201 Silicon Errata SPRZ153

Advisory 2.1.6

Revision(s) Affected:

Details:

Workaround:

McBSP: DXR to XSR Copy Not Generated (Continued)

(c)For byte-size writes with right justification on receive data:

–ch_A: /* for transmit */

dst_address = DXR+3; /* 0x018C0007 for McBSP0 or 0x01900007 for McBSP1 */ Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 1

–ch_B : /* for receive */

src_address = DRR+3 /* 0x018C0003 for McBSP0 or 0x01900003 for McBSP1 */ dst_address = mem_in;

Element_size = BYTE;

Address_inc_mode = = inc_by_ element_size

/* inc_by_index whose value is as specified for ch_A above will also work */

(d)For byte-size writes with left justification on receive data:

–Same as 2(c) above EXCEPT for: ch_B : /* for receive */ src_address = DRR;

DMA Split-mode End-of-frame Indexing

2.1 and 2.0

If a DMA channel is configured to do a multiframe split-mode transfer, both the Receive and Transmit transfers will generate an end-of-frame condition. This will cause the FRAME COND bit to be set multiple times per frame in the Secondary Control Register of the channel.

Also, if DST_DIR = Index (11b), the end-of-frame condition by both the Receive and Transmit Transfers will cause a destination address to be incremented using Frame Index, rather than Element Index. The problem is that both the last element in a frame for the Receive Read Transfer (split source to destination) and the last element in a frame for the Transmit Write Transfer (source to split destination) will cause the destination address to be indexed using the frame index. This should only occur for the last element in a frame for the Receive Read Transfer. (Internal reference number 0559)

If the FRAME COND bit is used to generate an interrupt to the CPU and/or the frame index and the element index on the destination address are not the same for a split-mode transfer, use two DMA channels.

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