38
C.7 Interrupt status register — BASE+20H
Table C-6 PCI-1784 Register for interrupt status
1514131211109876543210
Base Addr. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Interrupt status
DI3 DI2 DI1 DI0 IX3 IX2 IX1 IX0 UN3 UN2 UN1 UN0 OV3 OV2 OV1 OV0
20H R
IF TM UC3 UC2 UC1 UC0 OC3 OC2 OC1 OC0
OVn Counter overflow interrupt flag (n: 0 ~ 3)
0Disable
1Enable
UNnCounter underflow interrupt flag (n: 0 ~ 3)
0Disable
1Enable
IXnIndex input interrupt flag (n: 0 ~ 3)
0Disable
1Enable
DIn Digital input interrupt flag (n: 0 ~ 3)
0Disable
1Enable
OCnCounter over compare interrupt by flag (n: 0 ~ 3)
0Disable
1Enable
UCn Counter under compare interrupt flag (n: 0 ~ 3)
0Disable
1Enable
TM Timer pulse interrupt flag
0Disable
1Enable
IF Overall interrupt enable flag
0Disable
1Enable