Interrupt status register BASE+20H | Advantech PCI-1784 specification

C.7 Interrupt status register — BASE+20H

Table C-6 PCI-1784 Register for interrupt status

Base Addr.		15	14	13	12	11	10	9		8	7	6	5	4	3	2	1	0

		31	30	29	28	27	26	25		24	23	22	21	20	19	18	17	16
		31	30	29	28	27	26	25		24	23	22	21	20	19	18	17	16

									Interrupt status
20H	R
20H	R	DI3	DI2	DI1	DI0	IX3	IX2	IX1		IX0	UN3	UN2	UN1	UN0	OV3	OV2	OV1	OV0

		IF			TM						UC3	UC2	UC1	UC0	OC3	OC2	OC1	OC0

OVn	Counter overflow interrupt flag (n: 0 ~ 3)
	0	Disable
	1	Enable
UNn	Counter underflow interrupt flag (n: 0 ~ 3)
	0	Disable
	1	Enable
IXn	Index input interrupt flag (n: 0 ~ 3)
	0	Disable
	1	Enable
DIn	Digital input interrupt flag (n: 0 ~ 3)
	0	Disable
	1	Enable
OCn	Counter over compare interrupt by flag (n: 0 ~ 3)
	0	Disable
	1	Enable
UCn	Counter under compare interrupt flag (n: 0 ~ 3)
	0	Disable
	1	Enable
TM	Timer pulse interrupt flag
	0	Disable
	1	Enable
IF	Overall interrupt enable flag
	0	Disable
	1	Enable

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Image 42

Advantech specifications Interrupt status register BASE+20H, Table C-6 PCI-1784 Register for interrupt status

Contents

Page Page Contents Appendix D. Operation Features IntroductionEncoder Interface Flexible Digital Output function CountersDigital Input and Interrupts Special Shielded Cable for Noise Reduction Board ID Installation Guide Applications Installation Flow Chart Software Overview Device DriversRegister-level Programming Device Drivers Programming Roadmap Programming Tools Troubleshooting Device Drivers Error Programming with Device Drivers Function Library Accessories Wiring CableWiring Boards Installation UnpackingPage Driver Installation Setup Screen of Advantech Automation Software Hardware Installation Select the Individual Drivers optionPage Device name listed on the Device Manager Device Setup & Configuration Board selection Setting Up and configure the device ‘Setup’ dialog box Operation dialog box Overview Signal ConnectionsSwitch and Jumper Settings Names of Jumpers Function description Board ID setting SW1 Signal Connections Connector Signal DescriptionPin Assignment Quadrature encoder input Single ended Outputs Encoder Quadrature encoder up/down counter input connections Isolated digital input Isolated digital output Appendix A. Specifications TimerEncoder Output Interrupt Counter LatchGeneral Appendix B. Block Diagram ADDRESS, Control and Data BUSPage Appendix C. Register Structure and Format I/O Port Address Map Table C-1 PCI-1784 register format Part + HEX 1CH Clock Control Counter 0/1/2/3 mode BASE+00/04/08/0CH Table C-2 PCI-1784 Register for counter 0/1/2/3 mode DI0 Counter 0/1/2/3 latch data BASE+00/04/08/0CH Table C-3 PCI-1784 Register for counter 0/1/2/3 latch data Counter 0/1/2/3 compare data BASE+10/14/18/1CH Table C-4 PCI-1784 Register for counter 0/1/2/3 compare data Interrupt control register BASE+20H Table C-5 PCI-1784 Register for interrupt control Interrupt status register BASE+20H Table C-6 PCI-1784 Register for interrupt status Clear Interrupt BASE+24H Table C-7 PCI-1784 Register for clock control Table C-8 PCI-1784 Register for clear interrupt Software latch BASE+28H Table C-9 PCI-1784 Register for software latch Board ID BASE+28H Table C-10 PCI-1784 Board ID data Reset counter BASE+2CH Table C-11 PCI-1784 Register for reset counter Digital output BASE+30H Table C-12 PCI-1784 Register for digital output Digital input/output BASE+30H Table C-13 PCI-1784 Register for digital input/outputPage Appendix D. Operation Quadrature encoder introduction Counter modes Mode Maximum input rate 8MHz 4MHz 2MHz 1MHzQuadrature input counter mode Single-ended vs. differential input Disabled mode Pulse modePulse/direction mode Digital noise filter Latch Latch modeClock frequency Maximum width Index latch Counter reset value Timer function Interrupt function