Appendix C. Register Structure and Format | Advantech PCI-1784

Appendix C. Register Structure and Format

C.1 Overview

The PCI-1784 is delivered with an easy-to-use 32-bit DLL driver for user programming under the Windows 2000/95/98/NT/ME/XP operating system. We advise users to program the PCI-1784 using the 32-bit DLL driver provided by Advantech to avoid the complexity of low-level programming by register.

The most important consideration in programming the PCI-1784 the register level is to understand the function of the card's registers. The information in the following sections is provided only for users who would like to do their own low-level programming.

C.2 I/O Port Address Map

The PCI-1784 requires 32 consecutive addresses in the PC's I/O space. The address of each register is specified as an offset from the card's base address. For example, BASE+0 is the card's base address and BASE+6 is the base address plus six bytes.

The table C-1 shows the function of each register of the PCI-1784 or driver and its address relative to the card's base address.

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Advantech PCI-1784 specifications Appendix C. Register Structure and Format, I/O Port Address Map

Contents

Page Page Contents Appendix D. Operation Features IntroductionEncoder Interface Digital Input and Interrupts CountersFlexible Digital Output function Special Shielded Cable for Noise Reduction Board ID Applications Installation Guide Installation Flow Chart Software Overview Device DriversRegister-level Programming Programming Tools Device Drivers Programming Roadmap Programming with Device Drivers Function Library Troubleshooting Device Drivers Error Accessories Wiring CableWiring Boards Unpacking InstallationPage Setup Screen of Advantech Automation Software Driver Installation Select the Individual Drivers option Hardware InstallationPage Device name listed on the Device Manager Board selection Device Setup & Configuration ‘Setup’ dialog box Setting Up and configure the device Operation dialog box Switch and Jumper Settings Signal ConnectionsOverview Names of Jumpers Function description Board ID setting SW1 Signal Connections Connector Signal DescriptionPin Assignment Single ended Outputs Encoder Quadrature encoder input Quadrature encoder up/down counter input connections Isolated digital output Isolated digital input Appendix A. Specifications TimerEncoder Output Interrupt Counter LatchGeneral ADDRESS, Control and Data BUS Appendix B. Block DiagramPage I/O Port Address Map Appendix C. Register Structure and Format + HEX Table C-1 PCI-1784 register format Part 1CH Clock Control Table C-2 PCI-1784 Register for counter 0/1/2/3 mode Counter 0/1/2/3 mode BASE+00/04/08/0CH DI0 Table C-3 PCI-1784 Register for counter 0/1/2/3 latch data Counter 0/1/2/3 latch data BASE+00/04/08/0CH Table C-4 PCI-1784 Register for counter 0/1/2/3 compare data Counter 0/1/2/3 compare data BASE+10/14/18/1CH Table C-5 PCI-1784 Register for interrupt control Interrupt control register BASE+20H Table C-6 PCI-1784 Register for interrupt status Interrupt status register BASE+20H Table C-7 PCI-1784 Register for clock control Clear Interrupt BASE+24H Table C-8 PCI-1784 Register for clear interrupt Table C-9 PCI-1784 Register for software latch Software latch BASE+28H Table C-10 PCI-1784 Board ID data Board ID BASE+28H Table C-11 PCI-1784 Register for reset counter Reset counter BASE+2CH Table C-12 PCI-1784 Register for digital output Digital output BASE+30H Table C-13 PCI-1784 Register for digital input/output Digital input/output BASE+30HPage Quadrature encoder introduction Appendix D. Operation Quadrature input counter mode Mode Maximum input rate 8MHz 4MHz 2MHz 1MHzCounter modes Single-ended vs. differential input Pulse/direction mode Pulse modeDisabled mode Digital noise filter Clock frequency Maximum width Latch modeLatch Index latch Timer function Counter reset value Interrupt function