Cabletron Systems SmartCell 6A000 A.1.2 CPU Module

Appendix A-2 SmartCell 6A000 User Guide
Hardware Components Features and Specifications
Fi
g
ure A-1 Front panel
A.1.2 CPU Module
The CPU module provides control, signaling, and LAN serve r f u nctions for the switch. A 32-bit RISC processor
(i960CF, 33 MHz) operates all switch software options.
An on-board Segmentation and Reassembly (SAR) ASIC provides rapid packet processing. A common DRAM bank
stores both CPU data structures and SAR processing buffers. Sixteen megabytes of DRAM is standard; 64 MB is
optional.
512 KB SRAM supports up to 4096 VCs routed through the CPU module.
NO SYNC DATA
NO SYNC DATA
1234
1234
6A-IOM-21-4 6A-IOM-22-4
FAIL
STATUS
POWER
RX ENET
TX ENET
S
Y
S
T
E
M
C
O
M
AC
NO SYNC DATA
NO SYNC DATA
1234
6A-IOM-22-4
1234
6A-IOM-21-4
BD
E
T
H
E
R
N
E
T
Console Terminal
(RJ-45) Ethernet Port (10Base-T)
FAIL
STATUS
POWER
RX DATA
TX DATA
NO SYNC
DATA
Ejector
Reset Button
Ejector
NO SYNC DATA