Cabletron Systems SmartCell 6A000 manual CPU Module, Figure A-1 Front panel

Hardware Components Features and Specifications

Ejector
			S	FAIL
			Y	STATUS
			S	POWER
			T
				RX ENET
Reset Button			E
			M	TX ENET
			1	1
		DATA	NO SYNC	DATA	NO SYNC
			2	2
	A	6A-IOM-	C	6A-IOM-
		22-4		21-4
			3	3
			4	4
				E
Console Terminal				T
	C			H
	O			E
				R
	M
(RJ-45)				N
				E
				T
		1			1
		DATA	NO SYNC	DATA	NO SYNC
		2			2
	B	6A-IOM-	D	6A-IOM-
		21-4		22-4
		3			3
		4			4
Ejector

Figure A-1 Front panel

FAIL

STATUS

POWER

RX DATA

TX DATA

	DATA
	NO SYNC
DATA	NO SYNC

Ethernet Port (10Base-T)

A.1.2 CPU Module

The CPU module provides control, signaling, and LAN server functions for the switch. A 32-bit RISC processor (i960CF, 33 MHz) operates all switch software options.

An on-board Segmentation and Reassembly (SAR) ASIC provides rapid packet processing. A common DRAM bank stores both CPU data structures and SAR processing buffers. Sixteen megabytes of DRAM is standard; 64 MB is optional.

512 KB SRAM supports up to 4096 VCs routed through the CPU module.

Appendix A-2 SmartCell 6A000 User Guide