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Cypress manual PRELIMINARY CY14B101LA, CY14B101NA, SRAM Read Cycle #2 CE and OE Controlled 3

Models: CY14B101NA CY14B101LA

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PRELIMINARY CY14B101LA, CY14B101NA

Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 15, 19]

Address

Address Valid

		tRC	tHZCE
CE		tACE
CE
		tAA
		tLZCE	t
			HZOE
OE		tDOE
OE
		tLZOE	tHZBE
BHE, BLE		tDBE
BHE, BLE
		tLZBE
Data Output	High Impedance		Output Data Valid
Data Output		tPU	Output Data Valid
		tPU	tPD
			tPD
ICC	Standby	Active
	Figure 8. SRAM Write Cycle #1: WE Controlled [3, 18, 19, 21]
		tWC
Address		Address Valid
		tSCE	tHA
CE
		tBW
BHE, BLE
		tAW
		tPWE
WE		tSA
		tSA
		tSD	tHD
Data Input			Input Data Valid
		tHZWE	tLZWE
Data Output	Previous Data	High Impedance
Data Output	Previous Data

Note

21. CE or WE must be > VIH during address transitions.

Document #: 001-42879 Rev. *B

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Cypress manual PRELIMINARY CY14B101LA, CY14B101NA, SRAM Read Cycle #2 CE and OE Controlled 3, + Feedback

Contents

PRELIMINARY CY14B101LA, CY14B101NA FeaturesLogic Block Diagram1, 2 Functional DescriptionTop View Pinouts44 - TSOP not to scaleCY14B101LA, CY14B101NA PRELIMINARY48-SSOP SRAM Write Device OperationSRAM Read AutoStore OperationSoftware RECALL Hardware RECALL Power UpSoftware STORE PowerNoise Considerations Preventing AutoStoreData Protection PRELIMINARYOperating Range DC Electrical CharacteristicsMaximum Ratings PRELIMINARY CY14B101LA, CY14B101NAThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsPRELIMINARY AC Switching CharacteristicsSwitching Waveforms CY14B101LA, CY14B101NAFigure 8. SRAM Write Cycle #1 WE Controlled 3, 18, 19 PRELIMINARY CY14B101LA, CY14B101NAFigure 7. SRAM Read Cycle #2 CE and OE Controlled 3 + FeedbackFigure 10. SRAM Write Cycle #3 BHE and BLE Controlled 3, 18 PRELIMINARY CY14B101LA, CY14B101NAFigure 9. SRAM Write Cycle #2 CE Controlled 3, 18, 19 + FeedbackPRELIMINARY AutoStore/Power Up RECALLSwitching Waveforms CY14B101LA, CY14B101NAPRELIMINARY Software Controlled STORE/RECALL CycleSwitching Waveforms CY14B101LA, CY14B101NAPRELIMINARY CY14B101LA, CY14B101NA Hardware STORE CycleSwitching Waveforms Write latch setTruth Table For SRAM Operations PRELIMINARY CY14B101LA, CY14B101NAPRELIMINARY Ordering InformationCY14B101LA, CY14B101NA PRELIMINARY Ordering Information continuedCY14B101LA, CY14B101NA CY14B101LA, CY14B101NA PRELIMINARYOrdering Information continued PRELIMINARY CY14B101LA, CY14B101NA Part Numbering NomenclatureCY 14 B 101L A-ZS 20 X C T Figure 16. 44-Pin TSOP II Package DiagramsPRELIMINARY CY14B101LA, CY14B101NA + FeedbackFigure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm Package Diagrams continuedPRELIMINARY CY14B101LA, CY14B101NA + FeedbackFigure 18. 48-Pin SSOP Package Diagrams continuedPRELIMINARY CY14B101LA, CY14B101NA Page 22 ofFigure 19. 32-Pin SOIC Package Diagrams continuedPRELIMINARY CY14B101LA, CY14B101NA Page 23 ofDocument Title CY14B101LA/CY14B101NA 1 Mbit 128K x 8/64K x 16 nvSRAM Document History PagePRELIMINARY CY14B101LA, CY14B101NA Document NumberWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products

Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 15, 19]

Figure 8. SRAM Write Cycle #1: WE Controlled [3, 18, 19, 21]

21. CE or WE must be > VIH during address transitions.