Sram Read Cycle #2 CE and OE Controlled 3, 15

PRELIMINARY CY14B101LA, CY14B101NA

Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 15, 19]

Address

Address Valid

		tRC	tHZCE
CE		tACE
CE
		tAA
		tLZCE	t
			HZOE
OE		tDOE
OE
		tLZOE	tHZBE
BHE, BLE		tDBE
BHE, BLE
		tLZBE
Data Output	High Impedance		Output Data Valid
Data Output		tPU	Output Data Valid
		tPU	tPD
			tPD
ICC	Standby	Active
	Figure 8. SRAM Write Cycle #1: WE Controlled [3, 18, 19, 21]
		tWC
Address		Address Valid
		tSCE	tHA
CE
		tBW
BHE, BLE
		tAW
		tPWE
WE		tSA
		tSA
		tSD	tHD
Data Input			Input Data Valid
		tHZWE	tLZWE
Data Output	Previous Data	High Impedance
Data Output	Previous Data

Note

21. CE or WE must be > VIH during address transitions.

Document #: 001-42879 Rev. *B

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Cypress CY14B101LA, CY14B101NA manual Sram Read Cycle #2 CE and OE Controlled 3, 15

Contents

Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor Corporation Top View PinoutsNot to scale Byte Low Enable, Active LOW. Controls DQ7 DQ0 Output Enable, Active LOW. The active LOWByte High Enable, Active LOW. Controls DQ15 DQ8 Power Supply Inputs to the Device .0V +20%, -10% Sram Write Device OperationSram Read AutoStore Operation A15 A09 Mode Power Hardware Recall Power UpMode Selection Software Store Data Protection Mode Selection A15 A09Preventing AutoStore Noise Considerations Operating Range DC Electrical CharacteristicsMaximum Ratings Range Thermal Resistance Data Retention and EnduranceCapacitance AC Test Conditions Parameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write Cycle Sram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min Max Description 20ns 25ns 45ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse Width Inputs/Outputs Mode Power Truth Table for x8 Configuration Inputs/Outputs Mode PowerTruth Table for x16 Configuration Truth Table For Sram Operations Ordering Information CY14B101LA-BA25XCT CY14B101LA-ZS25XCTCY14B101LA-ZS25XC CY14B101LA-BA25XC CY14B101LA-BA45XCT CY14B101LA-ZS45XCTCY14B101LA-ZS45XC CY14B101LA-BA45XC ZS Tsop Part Numbering NomenclatureCY 14 B 101L A-ZS 20 X C T Nvsram Package Diagrams Pin Tsop II Ball Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic GVCH/AESA Document HistoryUNC/PYRS GVCH/PYRS Sales, Solutions, and Legal Information USB

Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 15, 19]

BHE, BLE

Figure 8. SRAM Write Cycle #1: WE Controlled [3, 18, 19, 21]