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| PRELIMINARY | CY14B101LA, CY14B101NA | |||||||||
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AutoStore/Power Up RECALL |
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Parameters |
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| Description |
| 20 ns |
| 25 ns |
| 45 ns | Unit | |||||
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| Min |
| Max | Min |
| Max | Min |
| Max | |||||
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tHRECALL [27] |
| Power Up RECALL Duration |
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| 20 |
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| 20 |
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| 20 | ms | |||
tSTORE [23] |
| STORE Cycle Duration |
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| 8 |
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| 8 |
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| 8 | ms | |||
tDELAY [24] |
| Time Allowed to Complete SRAM Cycle |
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| 20 |
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| 25 |
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| 25 | ns | |||
VSWITCH |
| Low Voltage Trigger Level |
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| 2.65 |
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| 2.65 |
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| 2.65 | V | |||
tVCCRISE |
| VCC Rise Time | 150 |
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| 150 |
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| 150 |
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VHDIS[14] |
| HSB | Output Driver Disable Voltage |
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| 1.9 |
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| 1.9 |
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| 1.9 | V | ||
tLZHSB |
| HSB | To Output Active Time |
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| 5 |
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| 5 |
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| 5 | µs | ||
tHHHD |
| HSB | High Active Time |
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| 500 |
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| 500 |
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| 500 | ns | ||
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL[27]
VSWITCH |
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VHDIS |
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VVCCRISE | Note23 | t | Note23 | t |
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| STORE |
| STORE |
| tHHHD |
| tHHHD | Note26 |
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HSB OUT |
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| tDELAY |
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| tLZHSB |
| t |
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Autostore |
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| LZHSB |
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| tDELAY |
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POWER- |
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UP |
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RECALL | tHRECALL |
| tHRECALL |
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Read & Write
Inhibited
(RWI)
BROWN | Read & Write | POWER | ||
RECALL | OUT | RECALL |
| DOWN |
| Autostore |
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| Autostore |
Notes
22.tHRECALL starts from the time VCC rises above VSWITCH.
23.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
24.On a Hardware STORE, Software STORE / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.
25.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
26.HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: | Page 12 of 25 |
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