CY14B101LA-ZS25XCT, CY14B101LA-BA25XCT | Cypress CY14B101NA specification

					PRELIMINARY		CY14B101LA, CY14B101NA


	Ordering Information (continued)

	Speed	Ordering Code			Package	Package Type		Operating
	(ns)	Ordering Code			Diagram	Package Type		Range
	(ns)				Diagram			Range
	25	CY14B101LA-ZS25XCT			51-85087	44-pin TSOP II		Commercial

		CY14B101LA-ZS25XC			51-85087	44-pin TSOP II

		CY14B101LA-BA25XCT			51-85128	48-ball FBGA

		CY14B101LA-BA25XC			51-85128	48-ball FBGA

		CY14B101LA-SP25XCT			51-85061	48-pin SSOP

		CY14B101LA-SP25XC			51-85061	48-pin SSOP

		CY14B101LA-SZ25XCT			51-85127	32-pin SOIC

		CY14B101LA-SZ25XC			51-85127	32-pin SOIC

		CY14B101NA-ZS25XCT			51-85087	44-pin TSOP II

		CY14B101NA-ZS25XC			51-85087	44-pin TSOP II

		CY14B101NA-BA25XCT			51-85128	48-ball FBGA

		CY14B101NA-BA25XC			51-85128	48-ball FBGA

		CY14B101LA-ZS25XIT			51-85087	44-pin TSOP II		Industrial

		CY14B101LA-ZS25XI			51-85087	44-pin TSOP II

		CY14B101LA-BA25XIT			51-85128	48-ball FBGA

		CY14B101LA-BA25XI			51-85128	48-ball FBGA

		CY14B101LA-SP25XIT			51-85061	48-pin SSOP

		CY14B101LA-SP25XI			51-85061	48-pin SSOP

		CY14B101LA-SZ25XIT			51-85127	32-pin SOIC

		CY14B101LA-SZ25XI			51-85127	32-pin SOIC

		CY14B101NA-ZS25XIT			51-85087	44-pin TSOP II

		CY14B101NA-ZS25XI			51-85087	44-pin TSOP II

		CY14B101NA-BA25XIT			51-85128	48-ball FBGA

		CY14B101NA-BA25XI			51-85128	48-ball FBGA

Document #: 001-42879 Rev. *B

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Cypress manual CY14B101LA-ZS25XCT, CY14B101LA-BA25XCT, CY14B101LA-SP25XCT, CY14B101LA-SZ25XCT, CY14B101NA-ZS25XCT

Contents

Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor Corporation Not to scale PinoutsTop View Byte High Enable, Active LOW. Controls DQ15 DQ8 Output Enable, Active LOW. The active LOWByte Low Enable, Active LOW. Controls DQ7 DQ0 Power Supply Inputs to the Device .0V +20%, -10% Sram Read Device OperationSram Write AutoStore Operation Mode Selection Hardware Recall Power UpA15 A09 Mode Power Software Store Preventing AutoStore Mode Selection A15 A09Data Protection Noise Considerations Maximum Ratings DC Electrical CharacteristicsOperating Range Range Capacitance Data Retention and EnduranceThermal Resistance AC Test Conditions Switching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write Cycle Sram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up Recall Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Hardware Store Cycle To Output Active Time when write latch not setDescription 20ns 25ns 45ns Unit Min Max Hardware Store Pulse Width Truth Table for x16 Configuration Truth Table for x8 Configuration Inputs/Outputs Mode PowerInputs/Outputs Mode Power Truth Table For Sram Operations Ordering Information CY14B101LA-ZS25XC CY14B101LA-ZS25XCTCY14B101LA-BA25XCT CY14B101LA-BA25XC CY14B101LA-ZS45XC CY14B101LA-ZS45XCTCY14B101LA-BA45XCT CY14B101LA-BA45XC CY 14 B 101L A-ZS 20 X C T Part Numbering NomenclatureZS Tsop Nvsram Pin Tsop II Package Diagrams Ball Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic UNC/PYRS Document HistoryGVCH/AESA GVCH/PYRS USB Sales, Solutions, and Legal Information